Devices and methods for enhancing insertion loss performance of an antenna switch

Patent metadata

Field	Value
Publication number	US-11855012-B2
Application number	US-202217713907-A
Country	US
Kind code	B2
Filing date	Apr 5, 2022
Priority date	Mar 29, 2018
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
providing a substrate comprising a plurality of regions each of which has a ring shape;
forming a metal-oxide-semiconductor device extending into the substrate; and forming a
plurality of contact pads on a surface of the substrate, wherein each of the plurality of contact pads corresponds to one of the plurality of regions,
wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad.

2. The method of claim 1 , wherein each of the plurality of contact pads has an area smaller than 4 square micrometers.

3. The method of claim 2 , wherein each of the plurality of contact pads has a shape covering a portion of the ring shape of the corresponding region.

4. The method of claim 1 , wherein a distance from the first contact pad to the second contact pad is larger than 0.01 micrometer.

5. The method of claim 1 , wherein a distance from the first contact pad to the second contact pad is smaller than 5 micrometers.

6. The method of claim 1 , wherein a distance from the second contact pad to the third contact pad is larger than 0.01 micrometer.

7. The method of claim 1 , wherein a distance from the second contact pad to the third contact pad is smaller than 200 micrometers.

8. The method of claim 1 , wherein the semiconductor device serves as an antenna switch.

9. A method for forming a semiconductor device, comprising:
providing a substrate comprising a plurality of regions each of which has a ring shape, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad;
forming a metal-oxide-semiconductor device extending into the substrate; and
forming at least one isolation feature extending into the substrate and disposed adjacent to the metal-oxide-semiconductor device.

10. The method of claim 9 , comprising forming at least four metal layers on the metal-oxide-semiconductor device in a chip portion of the semiconductor device.

11. The method of claim 10 , wherein a quantity of the at least four metal layers is between four and twenty.

12. The method of claim 11 , wherein an insertion loss of the semiconductor device is smaller as a quantity of the at least four metal layers becomes larger.

13. The method of claim 10 , wherein eight metal layers in total are formed on the metal-oxide-semiconductor device in the chip portion of the semiconductor device.

14. The method of claim 9 , further comprising:
forming at least one metal layer in a packaging portion of the semiconductor device.

15. The method of claim 14 , wherein an insertion loss of the semiconductor device is smaller as a quantity of the at least one metal layer becomes larger.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jin Jun-De

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title