Devices and methods for enhancing insertion loss performance of an antenna switch

US10861804B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10861804-B2
Application numberUS-201916364439-A
CountryUS
Kind codeB2
Filing dateMar 26, 2019
Priority dateMar 29, 2018
Publication dateDec 8, 2020
Grant dateDec 8, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device formed to serve as an antenna switch, comprising: an intrinsic substrate comprising a plurality of regions, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate, wherein the at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device. 2. The semiconductor device of claim 1 , wherein the at least one isolation feature comprises a shallow trench isolation. 3. The semiconductor device of claim 1 , wherein the intrinsic substrate comprises a material that has a higher impedance than that of an extrinsic semiconductor. 4. The semiconductor device of claim 1 , wherein the intrinsic substrate comprises non-doped silicon extending at least 20 micrometers from the metal-oxide-semiconductor device. 5. A semiconductor device formed to serve as an antenna switch, comprising: a substrate comprising a plurality of regions each of which has a ring shape; a metal-oxide-semiconductor device extending into the substrate; and a plurality of contact pads exposed on a surface of the substrate, wherein each of the plurality of contact pads corresponds to one of the plurality of regions and has a shape covering a portion of the ring shape of the corresponding region, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad. 6. The semiconductor device of claim 5 , wherein each of the plurality of contact pads has an area smaller than 4 square micrometers. 7. The semiconductor device of claim 5 , wherein: a distance from the first contact pad to the second contact pad is between 0.01 micrometer and 5 micrometers. 8. The semiconductor device of claim 5 , wherein: a distance from the second contact pad to the third contact pad is between 0.01 micrometer and 200 micrometers. 9. A semiconductor device formed to serve as an antenna switch, comprising: a first number of at least one transistor that are connected in parallel along a first direction when the first number is greater than one, wherein: each of the at least one transistor comprises a plurality of gate fingers; each of the plurality of gate fingers has a finger width extending along a second direction orthogonal to the first direction; the at least one transistor has a total finger width equal to a sum of all finger widths of all gate fingers of the at least one transistor; and the first number is minimized to one to remove spacing between every two adjacent transistors given the same total finger width. 10. The semiconductor device of claim 9 , further comprising: an electric line connecting to the at least one transistor along the second direction. 11. The semiconductor device of claim 9 , wherein: each of the plurality of gate fingers has a finger width of 2 micrometers. 12. The semiconductor device of claim 10 , wherein a total length of the at least one transistor along the first direction is closer to a thickness of the electric line after the first number is minimized. 13. The semiconductor device of claim 12 , wherein an insertion loss of the semiconductor device is smaller as the total length of the at least one transistor becomes closer to the thickness of the electric line. 14. A semiconductor device formed to serve as an antenna switch, comprising: a substrate comprising a plurality of regions, wherein the plurality of regions comprises at least one of: a p-type well region corresponding to a first contact pad, a deep n-type well region corresponding to a second contact pad, and a p-type substrate region corresponding to a third contact pad; a metal-oxide-semiconductor device extending into the substrate; at least one isolation feature extending into the substrate and disposed adjacent to the metal-oxide-semiconductor device; and at least four metal layers disposed on the metal-oxide-semiconductor device in a chip portion of the semiconductor device. 15. The semiconductor device of claim 14 , wherein a quantity of the at least four metal layers is between four and twenty. 16. The semiconductor device of claim 14 , further comprising: at least one metal layer formed in a packaging portion of the semiconductor device. 17. The semiconductor device of claim 15 , wherein an insertion loss of the semiconductor device is smaller as the quantity of the at least four metal layers becomes larger. 18. The semiconductor device of claim 16 , wherein an insertion loss of the semiconductor device is smaller as a quantity of the at least one metal layer becomes larger.

Assignees

Inventors

Classifications

  • Layouts of interconnections · CPC title

  • H10W44/20Primary

    at high-frequency [HF] or radio frequency [RF] · CPC title

  • of only insulated-gate FETs [IGFET] · CPC title

  • Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

  • Top-view geometrical layouts of the regions or the junctions · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10861804B2 cover?
Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic subst…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W44/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).