Semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-9954088-B2
Application number	US-201415029835-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	Oct 18, 2013
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device comprising the steps of:
growing a first nucleation layer and a second nucleation layer on a substrate;
depositing a first epitaxial layer and a second epitaxial layer over the first and second nucleation layers to form a channel layer comprising portions of the first and second epitaxial layers;
depositing a third epitaxial layer on the second epitaxial layer;
depositing a binary layer over the first and second nucleation layers;
depositing a thin spacer layer via chemical vapor deposition and etching the thin spacer layer to form a thin spacer located between the binary layer and the third epitaxial layer;
annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device.

2. The method of claim 1 ,
wherein the binary layer is deposited over the first, second and third epitaxial layers, and wherein the annealing step comprises:
annealing the binary layer with the first, second or third epitaxial layer to form the first contact area and the second contact area on the first, second or third epitaxial layer,
preferably wherein the first and second nucleation layers are grown by depositing at least one layer of aluminum nitride, wherein each of the at least one layer of aluminum nitride is deposited at different temperatures or pressures, and
preferably wherein the first epitaxial layer deposited is gallium nitride, the second epitaxial layer deposited is aluminum gallium nitride, and/or the third epitaxial layer deposited is gallium nitride, and
preferably wherein the channel layer between the second and the first epitaxial layer is a two-dimensional electron gas (2DEG) layer.

3. The method of claim 2 , further comprising the step of depositing a dielectric layer on the third epitaxial layer before annealing the binary layer with the first epitaxial layer,
preferably further comprising the step of depositing a CMOS compatible metal layer on the dielectric layer, and
preferably further comprising the steps of patterning a photo-resist layer on the CMOS compatible metal layer, etching the photo-resist layer to form a CMOS compatible metal gate structure, and stripping any residual photo-resist after etching.

4. The method of claim 3 , further comprising the step of etching the dielectric layer, the second and third epitaxial layers to expose the channel layer and to form a gate structure in the dielectric layer, the second and third epitaxial layers,
preferably further comprising the step of depositing a metal layer having a group 14 element selected from Si, Ge and their combination thereof, at 400° C. to 850° C. to cover the gate structure formed from the compatible metal layer, the dielectric layer, the second and third epitaxial layers, and
preferably wherein the deposition of the metal layer comprising Si, Ge or their combination thereof, occurs at 400° C. to 800° C., and
preferably further comprising the steps of depositing a thick spacer layer and etching the thick spacer layer to form a thick spacer on both sides of the gate structure formed from the compatible metal layer, the dielectric layer, the second and third epitaxial layers for forming the gate electrode.

5. The method of claim 1 , comprising the step of depositing an ultrathin spacer layer between the first epitaxial layer and the second epitaxial layer, and
optionally further comprising forming a gate electrode between the first and second contact areas before or after the annealing of the binary layer with the first, second or third epitaxial layer.

6. The method of claim 1 , further comprising the step of isolating the device via shallow trench isolation, mesa isolation or deposition of field oxides.

7. The method of claim 1 , wherein a CMOS compatible metal selected from the group of Ta, TaN, Ti, TiN, Ni, Co, Al, W, WN, any non-gold based metal and their combination thereof, is deposited on the metal layer having a group 14 element selected from Si, Ge and their combination thereof, to form the binary layer, and the binary layer is annealed with the first epitaxial layer to form the first and second contact areas with the gate electrode disposed between the first and second contact areas on the first epitaxial layer,
preferably wherein the annealing of the binary layer with the first epitaxial layer to form the first and second contact areas occurs at 400° C. to 1200° C.

8. The method of claim 1 , further comprising the steps of patterning a photo-resist on the third epitaxial layer and etching the photo-resist, the first, second and third epitaxial layers to form an island,
preferably further comprising the steps of stripping the photo-resist and depositing a silicon nitride, silicon oxide, silicon-oxynitride or Al 2 O 3 layer which is capable of acting as a field insulator layer surrounding the island, and
preferably further comprising the step of depositing a gate insulating layer selected from Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , Ta-doped Al 2 O 3 , HfAlO, La 2 O 3 , Si 3 N 4 , SiON, Y 2 O 3 , HfSiO 4 , SrTiO 2 , LaAlO 3 and SiO 2 , and
preferably further comprising the steps of patterning a photo-resist and etching the gate insulator layer without leading to any recesses, or further partially etching the second and/or third epitaxial layer on the island to form at least two recesses for the first and second contact on the island.

9. The method of claim 8 , further comprising the step of depositing a metal layer having a group 14 element selected from Si, Ge and their combination thereof, to cover the at least two recesses or the second and/or third epitaxial layer which is exposed after etching the gate insulator layer on the island,
preferably wherein the deposition of the metal layer comprising Si, Ge or their combination thereof, occurs at a temperature in the range of 273 K to about 350 K, and
preferably wherein a CMOS compatible metal selected from the group of Ta, TaN, Ti, TiN, Ni, Co, Al, W, WN, any non-gold based metal and their combination thereof, is deposited on the metal layer having a group 14 element selected from Si, Ge and their combination thereof, to form the binary layer in the at least two recesses or over the exposed second and/or third epitaxial layer, and the gate electrode is formed on the island between the first and second contact areas after the binary layer is annealed with the second and/or third epitaxial layer to form the first and second contact areas, and
preferably wherein the annealing of the binary layer with the second or third epitaxial layer to form the first and second contact areas occurs at 400° C. to 1200° C.

10. The method of claim 1 , wherein the substrate is a sapphire substrate, a silicon substrate, a silicon on insulator substrate or a silicon carbide substrate, and
optionally wherein the semiconductor device is selected from a group consisting of field effect transistors, high electron mobility transistors, inverters, power switches, power transistor devices, radio switches and radio-frequency based devices.

Assignees

• Agency Science Tech & Res

Inventors

• Bera Lakshmi Kanta
• Dolmanan Surani Bin
• Kumar Manippady Krishna
• Kajen Rasanayagam Sivasayan
• Tripathy Sudhiranjan

Classifications

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/287

  by chemical means · CPC title