Method of manufacturing a wiring substrate

Patent metadata

Field	Value
Publication number	US-10117336-B2
Application number	US-201514922972-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Sep 27, 2011
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

First claim

What is claimed is:

1. A method of manufacturing a wiring substrate, comprising:
forming a resist in which an opening portion is provided, on a supporting plate;
forming a concave portion in the supporting plate through the opening portion of the resist;
forming a metal layer for a connection pad in the concave portion of the supporting plate and the opening portion of the resist, by an electroplating utilizing the supporting plate as a plating power feeding path;
removing the resist;
after removing the resist,
forming a ring-like part of the supporting plate around an outer periphery part of the metal layer as a convex level difference portion whose height is higher than other etched surfaces, by etching the supporting plate while using the metal layer as a mask;
forming an insulating layer covering the metal layer, on the supporting plate; and
exposing the metal layer by removing the supporting plate.

2. A method of manufacturing a wiring substrate, according to claim 1 , after the removing of the resist, and before the removing of the supporting plate, further comprising:
forming an n-layer (n is an integer of 1 or more) wiring layer connected to the connection pad, on the supporting plate.

3. A method of manufacturing a wiring substrate, according to claim 1 , wherein the supporting plate is formed of copper,
the metal layer for the connection pad includes a barrier metal layer and a copper layer in sequence from a bottom, and
in the removing of the supporting plate, the supporting plate is removed selectively to the barrier metal layer.

4. A method of manufacturing a wiring substrate, according to claim 3 , after the removing of the supporting plate, further comprising:
removing the barrier metal layer selectively to the copper layer.

5. A method of manufacturing a wiring substrate, according to claim 3 , wherein the barrier metal layer is selected from the group consisting of a single layer film formed of a gold layer, a single layer film formed of a silver layer, a single layer film formed of a palladium layer, a single layer film formed of a nickel layer, in sequence from a bottom, a laminated film formed of a gold layer/a nickel layer, a laminated film formed of a gold layer/a palladium layer/a nickel layer, a laminated film formed of a gold layer/a silver layer/a palladium layer/a nickel layer, a laminated film formed of a silver layer/a nickel layer, and a laminated film formed of a silver layer/a palladium layer/a nickel layer.

6. A method of manufacturing a wiring substrate, according to claim 1 , wherein, in the forming the concave portion in the supporting plate, the concave portion is formed with a size bigger than the opening portion of the resist.

7. A method of manufacturing a wiring substrate, according to claim 1 , wherein, in forming the metal layer for the connection pad, a barrier metal layer is formed in the concave portion of the supporting plate, and a copper layer is formed in the opening portion of the resist.

8. A method of manufacturing a wiring substrate, according to claim 1 , wherein, the etching the metal layer and the supporting plate includes that each surface of the supporting plate and the metal layer is made into a roughened surface.

9. A method of manufacturing a wiring substrate, according to claim 1 , wherein, the metal layer is formed from a lower layer part whose side face and lower face are buried in the supporting plate, and an upper layer part whose side face and upper face are exposed from the supporting plate, a diameter of the upper layer part being smaller than a diameter of the lower layer part.

Assignees

• Shinko Electric Ind Co

Inventors

• Kaneko Kentaro
• Omiya Toshimitsu
• Kodani Kotaro
• Nakamura Junichi
• Kobayashi Kazuhiro

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/301

  for alignment · CPC title

• H10W72/07236

  Soldering or alloying · CPC title