Method for detecting defects in semiconductor device

Patent metadata

Field	Value
Publication number	US-11854913-B2
Application number	US-202117397416-A
Country	US
Kind code	B2
Filing date	Aug 9, 2021
Priority date	Aug 29, 2018
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

First claim

What is claimed is:

1. A method for detecting defects in a semiconductor device, comprising:
singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices;
providing a first bump and a second bump respectively on the first probe pad and the second probe pad;
probing the first probe pad and the second probe pad through the first bumps and the second bump to determine a connection status of the detecting devices; and
recognizing a defect when the connection status of the detecting devices indicates an open circuit.

2. The method of claim 1 , wherein the connection status of the detecting devices is determined by providing a test signal to the first probe pad, and detecting the test signal at the second probe pad.

3. The method of claim 1 , wherein each of the detecting devices comprises:
a plurality of connection structures;
a plurality of top conductive layers; and
a plurality of bottom conductive layers;
wherein the top conductive layers and the bottom conductive layers are alternately arranged between the connection structures.

4. A method for detecting defects in a semiconductor device, comprising:
receiving a die comprising at least a detecting device, a first probe pad and a second probe pad electrically connected to two ends of the detecting device;
forming a first bump and a second bump respectively on the first probe pad and the second probe pad;
providing a test signal to the first probe pad, and detecting the test signal at the second probe pad to determine a connection status of the detecting device; and
recognizing a defect when the connection status of the detecting device indicates an open circuit.

5. The method of claim 4 , wherein the die has a circuit region and an outer border, and the detecting device is disposed between the circuit region and the outer border.

6. The method of claim 5 , wherein the die further comprises a seal ring.

7. The method of claim 6 , wherein the seal ring is disposed between the outer border and the detecting device.

8. The method of claim 4 , wherein the test signal is provided prior to the forming of the first bump and the second bump.

9. The method of claim 4 , wherein the test signal is provided to the first probe pad through the first bump and to the second probe pad through the second bump.

10. The method of claim 4 , further comprising:
disposing a molding to encompass the die;
forming a redistribution layer over the die and the molding; and
forming at least a first conductor and at least a second conductor over the redistribution layer, wherein the first conductor is electrically connected to the first probe pad, and the second conductor is electrically connected to the second probe pad.

11. The method of claim 10 , wherein the test signal is provided to the first probe pad and the second probe pad through the redistribution layer, the first conductor and the second conductor.

12. A method for detecting defects in a semiconductor device, comprising:
receiving a die comprising at least a detecting device, a first pad and a second pad electrically connected to two ends of the detecting device;
disposing a molding to encompass the die, wherein the at least detecting device is separated from the molding;
forming a redistribution layer over the die and the molding;
forming at least a first conductor electrically connected to the first pad and a second conductor electrically connected to the second pad;
providing a test signal to the first pad;
detecting the test signal at the second pad to determine a connection status of the detecting device; and
recognizing a defect when the connection status of the detecting devices indicates an open circuit.

13. The method of claim 12 , wherein the die has a circuit region and an outer border, and the detecting device is disposed between the circuit region and the outer border.

14. The method of claim 13 , wherein the die further comprises a seal ring.

15. The method of claim 14 , wherein the seal ring is disposed between the outer border and the detecting device.

16. The method of claim 14 , wherein the detecting device extend along the seal ring in a parallel fashion and are separated from the seal ring by a distance.

17. The method of claim 12 , wherein the test signal is provided to the first pad and the second pad prior to the disposing of the molding.

18. The method of claim 12 , wherein the test signal is provided to the first pad and the second pad through the first conductor, the second conductor, and the redistribution layer.

19. The method of claim 12 , wherein the at least detecting device comprises:
a plurality of connection structures;
a plurality of top conductive layers; and
a plurality of bottom conductive layers;
wherein the top conductive layers and the bottom conductive layers are alternately arranged between the connection structures.

20. The method of claim 19 , wherein each of the connection structures is located between one of the top conductive layers and one of the bottom conductive layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yang-Che
• Chou Wei-Yu
• Shue Hong-Seng
• Lin Chen-Hua
• Tseng Huang-Wen
• Liang Victor Chiang
• Liu Chwen-Ming

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title