Integrated circuit device structures and double-sided electrical testing

Patent metadata

Field	Value
Publication number	US-11854894-B2
Application number	US-202017112697-A
Country	US
Kind code	B2
Filing date	Dec 4, 2020
Priority date	Aug 26, 2016
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

First claim

What is claimed is:

1. A method of electrical testing an integrated circuit (IC) die, the method comprising:
contacting a first conductive pin of an electrical test apparatus to a back-side structure coupled to a first gate terminal of a dual gate transistor device through a back-side of the die;
contacting a second conductive pin of the electrical test apparatus to a front-side structure coupled through a front-side of the die while contacting the first conductive pin to the back-side structure, wherein the front-side structure provides electrical coupling to a second gate terminal of the dual gate transistor device; and
executing an electrical test algorithm on the die through at least both of the first and second conductive pins to generate electrical test data corresponding to the die.

2. The method of claim 1 , wherein:
a third conductive pin of the electrical test apparatus contacts a second front-side structure exposed through the front-side of the die that provides electrical coupling to a source terminal of the transistor device; and
a fourth conductive pin of the electrical test apparatus contacts a third front-side structure exposed through a front-side of the die that provides electrical coupling to a drain terminal of the transistor device.

3. The method of claim 2 , wherein:
the first conductive pin is one of a plurality of conductive pins of a first prober of the electrical test apparatus;
the second conductive pin is one of a plurality of conductive pins of a second prober of the electrical test apparatus; and
the third conductive pin is one of the plurality of conductive pins of the second prober.

4. The method of claim 2 , wherein
the first conductive pin is one of a plurality of conductive pins of a first prober of the electrical test apparatus; and
the second, third and fourth conductive pin are each one of a plurality of conductive pins of a second prober of the electrical test apparatus.

5. The method of claim 1 , wherein the front-side structure comprises a metallization structure of a first front-side metallization layer and contacting the front-side structure comprises contacting through an opening in a host substrate adjacent to the first front-side metallization layer.

6. The method of claim 1 , further comprising:
contacting a third conductive pin of the electrical test apparatus to a second back-side structure exposed through a back-side of a second die, wherein the second back-side structure provides electrical coupling to a second transistor terminal of a second transistor device of the second die; and
executing, while executing the electrical test algorithm, a second electrical test algorithm on the second die through at least the third conductive pin to generate second electrical test data corresponding to the second die.

7. The method of claim 6 , wherein:
the first conductive pin is one of a plurality of conductive pins of a first prober of the electrical test apparatus;
the second conductive pin is one of a plurality of conductive pins of a second prober of the electrical test apparatus; and
the third conductive pin is one of the plurality of conductive pins of the first prober.

8. The method of claim 1 , wherein:
the first conductive pin is one of a plurality of conductive pins of a first prober of the electrical test apparatus; and
the second conductive pin is one of a plurality of conductive pins of a second prober of the electrical test apparatus.

Assignees

• Intel Corp

Inventors

• Rao Valluri R
• Morrow Patrick
• Mehandru Rishabh
• Ingerly Doug
• Jun Kimin
• O'Brien Kevin
• Fischer Paul
• Liao Szuya S
• Block Bruce

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title