Caching streams of memory requests

Patent metadata

Field	Value
Publication number	US-11853223-B2
Application number	US-202117455343-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Feb 13, 2019
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.

First claim

What is claimed is:

1. A system comprising:
one or more integrated client devices, each client device being configured to generate memory requests, each memory request having a respective physical address and a respective page-level attribute of a respective page of a first memory to which the physical address belongs;
a cache configured to perform operations comprising:
allocating a dedicated portion of the cache to be dedicated to memory requests having a page-level attribute for a page in memory so that the memory requests for locations within the page in memory are cached in the dedicated portion of the cache;
receiving a memory request from one of the one or more integrated client devices, the memory request having the page-level attribute,
determining that the dedicated portion of the cache is dedicated to memory requests having the page-level attribute, and
in response, servicing the memory request using the portion of the cache dedicated to memory requests having the page-level attribute.

2. The system of claim 1 , wherein the system comprises multiple client devices and wherein the cache is configured to use page-level attributes of memory requests to dedicate different portions of the cache to different client devices.

3. The system of claim 1 , wherein the cache is configured to use page-level attributes of memory requests to dedicate different portions of the cache to instructions and data.

4. The system of claim 1 , wherein the cache is configured to use page-level attributes of memory requests to distinguish page table requests from other memory requests.

5. The system of claim 1 , wherein servicing the memory request using the dedicated portion of the cache for the page-level attribute comprises using a different replacement policy that applies to memory requests having the page-level attribute than another replacement policy for other memory requests.

6. The system of claim 1 , wherein determining that the portion of the cache is dedicated to memory requests having the page-level attribute comprises mapping the page-level attribute value to a particular partition identifier.

7. The system of claim 1 , wherein the cache is configured to service memory requests having different physical addresses occurring on different physical pages that have the same page-level attribute from a same dedicated cache portion for the page-level attribute.

8. The system of claim 1 , wherein each client device has a respective address translation module that is configured to convert a virtual address received from a software driver to a respective memory request having a respective physical address and a respective page descriptor, and wherein each client device is configured to update a page table to assign a particular page-level attribute value to a particular page.

9. The system of claim 8 , wherein the cache is configured to distinguish different memory requests using particular page-level attributes of page descriptors generated by the respective address translation modules of the client devices.

10. The system of claim 8 , wherein the address translation module is a memory management unit that is configured to perform a hardware walk of a page table in the first memory in order to perform address translation.

11. A method performed by a device comprising one or more integrated client devices and a cache, each client device being configured to generate memory requests, each memory request having a respective physical address and a respective page-level attribute of a respective page of a first memory to which the physical address belongs, the method comprising:
allocating, by the cache, a dedicated portion of the cache to be dedicated to memory requests having a page-level attribute for a page in memory so that the memory requests for locations within the page in memory are cached in the dedicated portion of the cache;
receiving, by the cache, a memory request from one of the one or more integrated client devices, the memory request having the page-level attribute;
determining, by the cache, that the dedicated portion of the cache is dedicated to memory requests having the page-level attribute; and
in response, servicing the memory request using the portion of the cache dedicated to memory requests having the page-level attribute.

12. The method of claim 11 , wherein the system comprises multiple client devices and wherein the cache is configured to use page-level attributes of memory requests to dedicate different portions of the cache to different client devices.

13. The method of claim 11 , wherein the cache is configured to use page-level attributes of memory requests to dedicate different portions of the cache to instructions and data.

14. The method of claim 11 , wherein the cache is configured to use page-level attributes of memory requests to distinguish page table requests from other memory requests.

15. The method of claim 11 , wherein servicing the memory request using the dedicated portion of the cache for the page-level attribute comprises using a different replacement policy that applies to memory requests having the page-level attribute than another replacement policy for other memory requests.

16. The method of claim 11 , wherein determining that the portion of the cache is dedicated to memory requests having the page-level attribute comprises mapping the page-level attribute value to a particular partition identifier.

17. The method of claim 11 , wherein the cache is configured to service memory requests having different physical addresses occurring on different physical pages that have the same page-level attribute from a same dedicated cache portion for the page-level attribute.

18. The method of claim 11 , wherein each client device has a respective address translation module that is configured to convert a virtual address received from a software driver to a respective memory request having a respective physical address and a respective page descriptor, and wherein each client device is configured to update a page table to assign a particular page-level attribute value to a particular page.

19. The method of claim 18 , wherein the cache is configured to distinguish different memory requests using particular page-level attributes of page descriptors generated by the respective address translation modules of the client devices.

20. The method of claim 18 , wherein the address translation module is a memory management unit that is configured to perform a hardware walk of a page table in the first memory in order to perform address translation.

Assignees

• Google Llc

Inventors

• Chamarty Vinod
• Dias Joao

Classifications

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/1054

  the data cache being concurrently physically addressed · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title