System-on-chip and method of operating the same

Patent metadata

Field	Value
Publication number	US-9880940-B2
Application number	US-201414203799-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 11, 2013
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A system on chip (SoC) includes a central processing unit (CPU), an intellectual property (IP) block, and a memory management unit (MMU). The CPU is configured to set a prefetch direction corresponding to a working set of data. The IP block is configured to process the working set of data. The MMU is configured to prefetch a next page table entry from a page table based on the prefetch direction during address translation between a virtual address of the working set of data and a physical address.

First claim

What is claimed is:

1. A system-on-chip (SoC), comprising:
a central processing unit (CPU) configured to set prefetch direction information and memory management unit (MMU) allocation information;
an intellectual property (IP) block configured to process at least one working set of data;
an MMU configured to store the prefetch direction information to be allocated for the at least one working set of data, and to translate a virtual address of the at least one working set of data corresponding to a request of the IP block into a physical address;
an address distributor configured to store the MMU allocation information and to allocate the MMU to perform the translation of the virtual address based on the MMU allocation information;
a memory device configured to store data and physical address information of the data, wherein the memory device comprises a page table having a plurality of page table entries,
wherein the MMU is further configured to prefetch a next page table entry to be accessed next from the page table based on the prefetch direction information,
wherein the at least one working set of data indicates a set of pages frequently referred to in the memory device by the IP block, or an amount of pages to be loaded from the IP block to the memory device; and
a bus interconnect configured to connect the MMU to the IP block based on identification (ID) information corresponding to the MMU,
wherein the ID information corresponding to the MMU is output to the MMU by the address distributor, and corresponds to the virtual address of the working set of data corresponding to the request based on the MMU allocation information.

2. The SoC of claim 1 , wherein the MMU comprises:
a translation lookaside buffer (TLB) configured to store mapping information between the virtual address and the physical address;
a special function register configured to store the prefetch direction information; and
a prefetch buffer configured to prefetch the next page table entry from the page table based on the prefetch direction information, and store the next page table entry.

3. The SoC of claim 1 , wherein each of the plurality of page table entries comprises a physical page address, an offset, and a prefetch direction field storing the prefetch direction, and the MMU is configured to prefetch the next page table entry based on the prefetch direction field.

4. The SoC of claim 1 , wherein each of the plurality of page table entries comprises a physical page number, an offset, and a prefetch target entry number field, and the MMU is configured to prefetch the next page table entry corresponding to the prefetch target entry number field.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kwan Ho
• Kim Seok Min

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F9/06 Primary

  using stored programs, i.e. using an internal store of processing equipment to receive or retain programs · CPC title