Semiconductor devices with package-level configurability

Patent metadata

Field	Value
Publication number	US-11848323-B2
Application number	US-202117178771-A
Country	US
Kind code	B2
Filing date	Feb 18, 2021
Priority date	Nov 13, 2017
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

First claim

We claim:

1. A semiconductor die, comprising:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element;
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements; and
a single solder ball in both direct physical and electrical contact with each of the first contact pad and the second contact pad.

2. The semiconductor die of claim 1 , wherein the first circuit is a driver circuit.

3. The semiconductor die of claim 1 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

4. The semiconductor die of claim 1 , further comprising a NAND memory array.

5. The semiconductor die of claim 1 , further comprising a wirebond directly coupled to the single solder ball.

6. The semiconductor die of claim 1 , wherein the first contact pad is separated from the second contact pad by a region of non-conductive material.

7. The semiconductor die of claim 6 , wherein the single solder ball bridges the region of non-conductive material.

8. The semiconductor die of claim 1 , further comprising a third contact pad electrically coupled to a third circuit on the semiconductor die including only passive circuit elements.

9. The semiconductor die of claim 8 , wherein the single solder ball is also in direct electrical and physical contact with the third contact pad.

10. The semiconductor die of claim 8 , wherein the third contact pad is separated from the first contact pad and the second contact pad by one or more regions of non-conductive material.

11. The semiconductor die of claim 10 , wherein the single solder ball bridges the one or more regions of non-conductive material.

12. The semiconductor die of claim 1 , wherein the single solder ball is a first single solder ball, and wherein the semiconductor die further comprises:
a third contact pad electrically coupled to a third circuit on the semiconductor die including at least one active circuit element;
a fourth contact pad electrically coupled to a fourth circuit on the semiconductor die including only passive circuit elements; and
a second single solder ball in both direct physical and electrical contact with each of the third contact pad and the fourth contact pad.

13. A method of packaging a semiconductor device assembly, comprising:
providing a semiconductor die including:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element, and
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements,
electrically coupling the first circuit to the second circuit with a single solder ball in both direct physical and electrical contact with the first contact pad and the second contact pad.

14. The method of claim 13 , wherein the first circuit is a driver circuit.

15. The method of claim 13 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

16. The method of claim 13 , wherein the semiconductor die comprises a NAND memory die.

17. The method of claim 13 , further comprising directly coupling a wirebond to the single solder ball.

18. The method of claim 13 , wherein the first contact pad is separated from the second contact pad by a region of non-conductive material, and wherein electrically coupling the first circuit to the second circuit comprises reflowing the single solder ball to bridge the region of non-conductive material.

19. The method of claim 13 , wherein the semiconductor die further comprises a third contact pad electrically coupled to a third circuit on the semiconductor die including only passive circuit elements, and wherein the method further comprises electrically coupling the third circuit to the first circuit and the second circuit with the single solder ball in both direct physical and electrical contact with the third contact pad.

20. A semiconductor device package, comprising:
a semiconductor die including:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element, and
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements;

a single solder ball in both direct physical and electrical contact with each of the first contact pad and the second contact pad; and
a wirebond electrically coupling the single solder ball to an exterior contact of the semiconductor device package.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Pusey John B
• Yin Zhiping
• Duesman Kevin G

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/07554

  changes in dispositions · CPC title