Integrated Circuit Structure with Active and Passive Devices in Different Tiers

Patent metadata

Field	Value
Publication number	US-2016254248-A1
Application number	US-201615151722-A
Country	US
Kind code	A1
Filing date	May 11, 2016
Priority date	Sep 9, 2013
Publication date	Sep 1, 2016
Grant date	—

Abstract

An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

First claim

What is claimed is:

1 . A method comprising:
forming a first-tier chip comprising:
forming first active devices at a surface of a semiconductor substrate; and
forming a first interconnect structure over the semiconductor substrate, wherein the first-tier chip is free from passive devices therein;
bonding an additional substrate over the first interconnect structure; forming a plurality of through-vias penetrating through the additional substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure; forming a second interconnect structure over the additional substrate; and forming a plurality of passive devices in the second interconnect structure, wherein the additional substrate, the plurality of through-vias, the second interconnect structure, and the plurality of passive devices in combination form a second-tier chip.

2 . The method of claim 1 further comprising, after the bonding the additional substrate and before the forming the plurality of through-vias, thinning the additional substrate.

3 . The method of claim 1 further comprising forming electrical connectors over, and electrically coupling to, the second interconnect structure.

4 . The method of claim 1 further comprising forming second active devices at a surface of the additional substrate.

5 . The method of claim 1 , wherein no active device exists at surfaces of the additional substrate after the second interconnect structure is formed.

6 . The method of claim 5 , wherein the additional substrate is an additional semiconductor substrate.

7 . The method of claim 5 , wherein the additional substrate is a dielectric substrate.

8 . The method of claim 1 , wherein:
the first-tier chip comprises a first plurality of low-k dielectric layers, with upper ones of the first plurality of low-k dielectric layers being no thinner than lower ones of the first plurality of low-k dielectric layers; and the second-tier chip comprises a second plurality of low-k dielectric layers, with an upper one of the second plurality of low-k dielectric layers being thinner than a lower one of the second plurality of low-k dielectric layers.

9 . A method comprising:
bonding a dielectric substrate to a dielectric layer of a chip, wherein the chip comprises:
a semiconductor substrate;
active devices at a surface of the semiconductor substrate;
a first interconnect structure over the semiconductor substrate, wherein the dielectric layer is a top one of the first interconnect structure;
forming a plurality of through-vias penetrating through the dielectric substrate, wherein the plurality of through-vias is in contact with metal pads in the dielectric layer; forming a second interconnect structure over the dielectric substrate; and forming a plurality of passive devices in the second interconnect structure, wherein the plurality of passive devices is electrically coupled to the plurality of through-vias.

10 . The method of claim 9 , wherein the chip is free from passive devices therein.

11 . The method of claim 9 , wherein the forming the second interconnect structure comprises forming a plurality of low-k dielectric layers, with an upper one of the plurality of low-k dielectric layers being thinner than a lower one of the plurality of low-k dielectric layers.

12 . The method of claim 11 , wherein the lower one of the plurality of low-k dielectric layers has one of the plurality of passive devices extending therein, and wherein the one of the plurality of passive devices is selected from the group consisting essentially of an inductor, a transformer, a transmission line, and combinations thereof.

13 . The method of claim 12 , wherein the forming the second interconnect structure further comprises:
forming a shielding layer over the lower one of the plurality of low-k dielectric layers; and electrically grounding a metal pad in the shielding layer, with the metal pad overlapping the one of the plurality of passive devices.

14 . The method of claim 11 , wherein the forming the plurality of passive devices comprises forming a capacitor in the upper one of the plurality of low-k dielectric layers.

15 . A method comprising:
forming a composite chip comprising:
forming a first-tier chip comprising:
forming active devices at a surface of a semiconductor substrate; and
forming a first interconnect structure over the semiconductor substrate, wherein the first-tier chip is free from passive devices therein; and

forming a second-tier chip comprising:
forming a second interconnect structure over a substrate, wherein the substrate is bonded to the first-tier chip;
forming a plurality of through-vias penetrating through the substrate; and
forming a plurality of passive devices in the second interconnect structure, wherein the plurality of passive devices is electrically coupled to the active devices through the plurality of through-vias.

16 . The method of claim 15 , wherein the forming the second-tier chip comprises:
bonding the substrate as a blank substrate to the first-tier chip; and thinning the blank substrate, with the plurality of through-vias formed in the thinned blank substrate.

17 . The method of claim 15 , wherein:
the first interconnect structure comprises a first plurality of low-k dielectric layers, with upper ones of the first plurality of low-k dielectric layers being no thinner than lower ones of the first plurality of low-k dielectric layers; and the second interconnect structure comprises a second plurality of low-k dielectric layers, with an upper one of the second plurality of low-k dielectric layers being thinner than a lower one of the second plurality of low-k dielectric layers.

18 . The method of claim 15 , wherein no active device is formed at surfaces of the substrate.

19 . The method of claim 15 , wherein the substrate is a semiconductor substrate.

20 . The method of claim 15 , wherein the substrate is a dielectric substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Yu-Nan

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title