Selective blocking of metal surfaces using bifunctional self-assembled monolayers

Patent metadata

Field	Value
Publication number	US-11848229-B2
Application number	US-202217971217-A
Country	US
Kind code	B2
Filing date	Oct 21, 2022
Priority date	Oct 27, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups, at least one functional group selected from amino groups, hydroxyl groups, ether linkages or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
selectively depositing a self-assembled monolayer (SAM) on a first surface of a substrate by exposing the substrate to a first precursor, wherein the substrate has at least one feature comprising the first surface and a second surface and wherein the first precursor has a structure of any of Formula (xiv), Formula (xvi), or Formula (xix) through Formula (xxvii)

wherein each n is independently 1-20 and each R is independently selected from H, C1-C10 alkyl or aryl groups;
selectively depositing a liner on the second surface by exposing the substrate to a second precursor; and
removing the self-assembled monolayer (SAM),
wherein the first surface comprises a metal, and the second surface comprises a dielectric material.

2. The method of claim 1 , wherein selectively depositing the self-assembled monolayer (SAM) comprises forming the SAM on the first surface and not on the second surface.

3. The method of claim 1 , wherein selectively depositing the liner comprises forming the liner on the second surface and not on the first surface.

4. The method of claim 1 , further comprising cleaning the substrate before depositing the self-assembled monolayer (SAM) to form a substrate surface substantially free of oxide.

5. The method of claim 1 , wherein the first surface comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo).

6. The method of claim 1 , further comprising depositing an adhesion layer on the first surface and on the liner after removing the self-assembled monolayer (SAM).

7. The method of claim 1 , wherein the at least one feature comprises one or more of a trench and a via.

8. The method of claim 1 , further comprising depositing a conductive material in the at least one feature by exposing the substrate to a third precursor, the third precursor comprising a metal.

9. The method of claim 8 , wherein depositing the conductive material comprises one or more of a bottom-up gap fill and a conformal gap fill.

10. The method of claim 1 , wherein the first precursor is substantially free from one or more of metal, halogen or nitrogen, the substantially free refers to a less than 5% weight on atomic basis.

11. The method of claim 1 , wherein the first precursor comprises at least one unsaturated group.

12. The method of claim 1 , wherein the first precursor comprises at least one hydroxyl group.

13. The method of claim 1 , wherein the first precursor comprises at least one ether group.

14. The method of claim 1 , wherein the first precursor comprises at least one amine group.

15. The method of claim 1 , wherein a first precursor has a molecular weight in a range of from 50 Daltons to 500 Daltons.

16. The method of claim 1 , wherein the first precursor has a vapor pressure in a range of from 100 mTorr to 100 Torr at 120° C.

17. A method of forming a semiconductor structure, the method comprising:
exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature comprising the first surface and a second surface;
exposing the substrate to a second precursor to selectively deposit a liner on the second surface; and
removing the self-assembled monolayer (SAM),

wherein the first surface comprises a metal selected from one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W) and molybdenum (Mo),
wherein the second surface comprises a dielectric material,
wherein the first precursor has a molecular weight in a range of from 50 Daltons to 500 Daltons, and
wherein the first precursor is selected from the group consisting of structures of Formula (xiv) or Formula (xvi)

wherein each n is independently 1-20 and each R is independently selected from H, C1-C10 alkyl or aryl groups.

18. A method of forming a semiconductor structure, the method comprising:
exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature comprising the first surface and a second surface;
exposing the substrate to a second precursor to selectively deposit a liner on the second surface; and
removing the self-assembled monolayer (SAM),

wherein the first surface comprises a metal selected from one or more of tungsten (W) and molybdenum (Mo),
wherein the second surface comprises a dielectric material,
wherein the first precursor has a vapor pressure in a range of from 100 mTorr to 100 Torr at 120° C., and
wherein the first precursor is selected from the group consisting of structures of Formula (xix) through Formula (xxvii)

wherein each R is independently selected from H, C1-C10 alkyl or aryl groups.

Assignees

• Applied Materials Inc

Inventors

• Mcswiney Michael L
• Bhuyan Bhaskar Jyoti
• Saly Mark
• Phillips Drew
• Dangerfield Aaron
• Thompson David
• Kashefi Kevin
• Xie Xiangjin

Classifications

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10P14/668

  the materials being characterised by the deposition precursor materials · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title