Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures

Patent metadata

Field	Value
Publication number	US-11848200-B2
Application number	US-202016885098-A
Country	US
Kind code	B2
Filing date	May 27, 2020
Priority date	May 8, 2017
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process is disclosed. The method may comprise contacting the substrate with a first reactant comprising a silicon halide source and contacting the substrate with a second reactant comprising a nitrogen source, wherein the incubation period for the first metallic surface is less than the incubation period for the second dielectric surface. Semiconductor device structures comprising a selective silicon nitride film are also disclosed.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a substrate comprising a first metallic surface and a second dielectric surface;
a silicon nitride film disposed on the first metallic surface and the second dielectric surface, wherein the first metallic surface has a first incubation period for silicon nitride and the second dielectric surface has a second incubation period for silicon nitride, wherein the silicon nitride film is formed by:
contacting the substrate with a first reactant comprising a silicon halide source;
contacting the substrate with a second reactant comprising a nitrogen source;
repeating the steps of contacting the substrate with the first reactant and contacting the substrate with the second reactant for the second incubation period for the second dielectric surface; and
repeating the steps of contacting the substrate with the first reactant and contacting the substrate with the second reactant for at least one cycle after the second incubation period for the second dielectric surface,

wherein the first incubation period for the first metallic surface is less than the second incubation period for the second dielectric surface,
wherein the silicon nitride film on the second dielectric surface has a thickness greater than 2 Angstroms, and
wherein the silicon nitride film is thicker on the first metallic surface than on the second dielectric surface.

2. The semiconductor device structure of claim 1 , wherein the first metallic surface comprises at least one of molybdenum (Mo), silicon (Si), silicon germanium (SiGe), germanium antimony tellurium (GeSbTe), cobalt (Co), tantalum silicide (TaSi), titanium silicide (TiSi), gallium arsenide (GaAs) or gallium nitride (GaN).

3. The semiconductor device structure of claim 1 , wherein the second dielectric surface comprises at least one of a silicon nitride, a silicon oxynitride, carbon, hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO) or silicon oxycarbide (SiOC).

4. The semiconductor device structure of claim 3 , wherein the second dielectric surface comprises more than about 30% silicon dioxide.

5. The semiconductor device structure of claim 3 , wherein the second dielectric surface comprises at least one of a silicon nitride surface and a silicon oxynitride surface.

6. The semiconductor device structure of claim 2 , wherein the second dielectric surface comprises germanium-oxide bonds.

7. The semiconductor device structure of claim 1 , wherein a thickness of the silicon nitride film disposed on the first metallic surface is less than 30 Angstroms.

8. The semiconductor device structure of claim 7 , wherein the thickness is less than 10 Angstroms.

9. The semiconductor device structure of claim 1 , wherein the second dielectric surface comprises a silicon oxide.

10. The semiconductor device structure of claim 9 , further comprising a diffusion barrier layer disposed between the copper interconnect and the second dielectric surface.

11. The semiconductor device structure of claim 10 , wherein the diffusion barrier layer comprises at least one of tantalum, tantalum nitride, tungsten, and tungsten nitride.

12. A reaction system, comprising:
a reaction chamber comprising the substrate of claim 1 ;
a first reactant source coupled to the reaction chamber and configured to deliver a silicon halide to the reaction chamber;
a second reactant source coupled to the reaction chamber and configured to deliver a nitrogen source to the reaction chamber,
wherein the reaction system is configured to provide an incubation period for the first metallic surface of the substrate that is less than an incubation period of the second dielectric surface of the substrate.

13. The reaction system of claim 12 , further comprising a purge gas source coupled to the reaction chamber.

14. The reaction system of claim 12 , further comprising a system operation and control mechanism electronically coupled to at least one of the reaction chamber, the first reactant source, or the second reactant source and configured to provide electronic circuitry and mechanical components to selectively operate at least one of the reaction chamber, the first reactant source, or the second reactant source.

15. The semiconductor device structure of claim 1 , wherein the first metallic surface comprises a metal oxide surface, a metal boride surface, or a semi-metal surface.

16. The semiconductor device structure of claim 1 , wherein the first metallic surface comprises a semi-metal surface.

17. The semiconductor device structure of claim 1 , wherein the second dielectric surface comprises —OH groups.

18. The semiconductor device structure of claim 1 , wherein a selectivity of the silicon nitride film on the first metallic surface to the second dielectric surface is greater than 80%.

Assignees

• Asm Ip Holding Bv

Inventors

• Woodruff Jacob
• Sharma Bed

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10P14/6339 Primary

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title