FeRAM with laminated ferroelectric film and method forming same

Patent metadata

Field	Value
Publication number	US-11844226-B2
Application number	US-202217818649-A
Country	US
Kind code	B2
Filing date	Aug 9, 2022
Priority date	Jul 23, 2020
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

First claim

What is claimed is:

1. A device comprising:
a Ferroelectric Random Access Memory (FeRAM) cell comprising:
a bottom electrode;
a laminate ferroelectric layer comprising:
a first amorphous ferroelectric layer over the bottom electrode;
a first polycrystalline ferroelectric layer over the first amorphous ferroelectric layer;
a second amorphous ferroelectric layer over the first polycrystalline ferroelectric layer; and
a second polycrystalline ferroelectric layer over the second amorphous ferroelectric layer; and

a top electrode over the second polycrystalline ferroelectric layer.

2. The device of claim 1 , wherein the first amorphous ferroelectric layer, the first polycrystalline ferroelectric layer, the second amorphous ferroelectric layer, and the second polycrystalline ferroelectric layer are high-k dielectric layers.

3. The device of claim 1 , wherein the first amorphous ferroelectric layer and the first polycrystalline ferroelectric layer comprise different materials.

4. The device of claim 1 , wherein the first amorphous ferroelectric layer and the second amorphous ferroelectric layer comprise a same material.

5. The device of claim 1 , wherein each of the first polycrystalline ferroelectric layer and the second polycrystalline ferroelectric layer comprises fewer than about 7 atomic layers.

6. The device of claim 1 , wherein the second amorphous ferroelectric layer comprises more than about 3 atomic layers.

7. The device of claim 1 , wherein the first amorphous ferroelectric layer comprises hafnium oxide, and the second amorphous ferroelectric layer comprises zirconium oxide.

8. The device of claim 1 , wherein both of the first amorphous ferroelectric layer and the second amorphous ferroelectric layer comprise zirconium oxide.

9. A device comprising:
a bottom electrode;
a first plurality of ferroelectric layers over the bottom electrode, wherein the first plurality of ferroelectric layers are formed of first materials having first crystallization temperatures;
a second plurality of ferroelectric layers over the bottom electrode, wherein the first plurality of ferroelectric layers and the second plurality of ferroelectric layers are stacked alternatingly, and wherein the second plurality of ferroelectric layers are formed of second materials having second crystallization temperatures, and the second crystallization temperatures are lower than the first crystallization temperatures; and
a top electrode over the first plurality of ferroelectric layers and the second plurality of ferroelectric layers.

10. The device of claim 9 , wherein the first plurality of ferroelectric layers are formed of a same first material, and the second plurality of ferroelectric layers are formed of a same second material.

11. The device of claim 10 , wherein the same first material is different from the same second material.

12. The device of claim 11 , wherein the same first material comprises hafnium oxide, and the same second material comprises zirconium oxide.

13. The device of claim 9 , wherein the first plurality of ferroelectric layers are amorphous layers, and the second plurality of ferroelectric layers are polycrystalline layers.

14. The device of claim 9 , wherein grains in each of the second plurality of ferroelectric layers are fully separated from additional grains in other ones of the second plurality of ferroelectric layers.

15. The device of claim 9 , wherein materials of the first plurality of ferroelectric layers and the second plurality of ferroelectric layers are configured such that a temperature difference between the first crystallization temperatures and the second crystallization temperatures is greater than about 50° C.

16. The device of claim 15 , wherein the materials of the first plurality of ferroelectric layers and the second plurality of ferroelectric layers are configured such that the temperature difference is between about 50° C. and about 300° C.

17. A device comprising:
a Ferroelectric Random Access Memory (FeRAM) cell comprising:
a bottom electrode;
a ferroelectric layer comprising:
a first amorphous ferroelectric layer over the bottom electrode;
a first polycrystalline ferroelectric layer over the first amorphous ferroelectric layer;
a second amorphous ferroelectric layer over the first polycrystalline ferroelectric layer, wherein the first polycrystalline ferroelectric layer form horizontal interfaces with both of the first amorphous ferroelectric layer and the second amorphous ferroelectric layer; and
a second polycrystalline ferroelectric layer over, and forming an additional horizontal interface with, the second amorphous ferroelectric layer; and

a top electrode over the ferroelectric layer.

18. The device of claim 17 , wherein the first amorphous ferroelectric layer and the first polycrystalline ferroelectric layer are formed of a same material.

19. The device of claim 17 , wherein the first amorphous ferroelectric layer and the first polycrystalline ferroelectric layer are formed of different materials.

20. The device of claim 19 , wherein the first amorphous ferroelectric layer has a first crystallization temperature, and the first polycrystalline ferroelectric layer has a second crystallization temperature lower than the first crystallization temperature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Bi-Shen
• Wei Yi Yang
• Lin Hsing-Lien
• Kuang Hsun-Chung
• Tsai Cheng-Yuan
• Trinh Hai-Dang

Classifications

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H10D1/692

  Electrodes · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10B53/30 Primary

  characterised by the memory core region · CPC title