Display apparatus

Patent metadata

Field	Value
Publication number	US-11839112-B2
Application number	US-202117370857-A
Country	US
Kind code	B2
Filing date	Jul 8, 2021
Priority date	Dec 18, 2020
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A display apparatus includes a substrate including a display area in which a display element is arranged, a first thin-film transistor arranged in the display area and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor, a first interlayer insulating layer covering the first gate electrode, a second thin-film transistor on the first interlayer insulating layer and including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer including an oxide semiconductor, and an upper electrode arranged on the first interlayer insulating layer and including a same material as that of the second semiconductor layer and at least overlapping the first gate electrode.

First claim

What is claimed is:

1. A display apparatus comprising:
a substrate including a display area in which a display element is arranged;
a first thin-film transistor arranged in the display area and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor;
a first interlayer insulating layer covering the first gate electrode;
a second thin-film transistor including a second semiconductor layer disposed on the first interlayer insulating layer and including an oxide semiconductor, a second gate electrode insulated from the second semiconductor layer, and a third gate electrode disposed between the substrate and the second semiconductor layer; and
an upper electrode arranged on the first interlayer insulating layer and including a same material as that of the second semiconductor layer and overlapping at least a portion of the first gate electrode,
wherein the third gate electrode at least partially overlaps the second semiconductor layer, and
wherein the third gate electrode is arranged on a same layer as the first gate electrode.

2. The display apparatus of claim 1 , further comprising a lower electrode arranged on a same layer as the first gate electrode,
wherein the lower electrode and the upper electrode constitute a capacitor.

3. The display apparatus of claim 2 , wherein the first gate electrode and the lower electrode are integrally formed.

4. The display apparatus of claim 1 , wherein at least a portion of the upper electrode is imparted with conductivity.

5. The display apparatus of claim 1 , wherein an opening having a closed shape is formed in the upper electrode.

6. The display apparatus of claim 1 , further comprising a first gate insulating layer covering the first semiconductor layer.

7. The display apparatus of claim 6 , wherein the third gate electrode is disposed on the first gate insulating layer.

8. The display apparatus of claim 1 , further comprising a second gate insulating layer disposed between the second semiconductor layer and the second gate electrode.

9. The display apparatus of claim 8 , further comprising a second interlayer insulating layer disposed on the second gate electrode.

10. The display apparatus of claim 9 , further comprising a first electrode arranged on the second gate insulating layer.

11. The display apparatus of claim 10 , further comprising a second electrode disposed on the second interlayer insulating layer and including one end electrically connected to the upper electrode and another end electrically connected to the first electrode.

12. The display apparatus of claim 11 , further comprising a planarization layer covering the second electrode,
wherein the display element includes an organic light-emitting diode arranged on the planarization layer.

13. A display apparatus comprising:
a substrate including a display area in which a display element is arranged;
a first thin-film transistor arranged in the display area and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor;
a first interlayer insulating layer covering the first gate electrode;
a second thin-film transistor including a second semiconductor layer disposed on the first interlayer insulating layer and including an oxide semiconductor, a second gate electrode insulated from the second semiconductor layer, and a third gate electrode disposed between the substrate and the second semiconductor layer; and
a capacitor including a lower electrode on a same layer as the first gate electrode and an upper electrode that is arranged on the first interlayer insulating layer, at least partially overlaps the lower electrode, and includes an oxide semiconductor,
wherein the third gate electrode at least partially overlaps the second semiconductor layer, and
wherein the third gate electrode is arranged on a same layer as the first gate electrode.

14. The display apparatus of claim 13 , wherein the first gate electrode and the lower electrode are integrally formed.

15. The display apparatus of claim 13 , wherein at least a portion of the upper electrode is imparted with conductivity.

16. The display apparatus of claim 13 , further comprising a second interlayer insulating layer disposed on the second gate electrode.

17. The display apparatus of claim 16 , further comprising:
a first electrode disposed on a same layer as the second gate electrode; and
a second electrode disposed on the second interlayer insulating layer and having one end electrically connected to the upper electrode and another end electrically connected to the first electrode.

18. The display apparatus of claim 13 , wherein the upper electrode and the second semiconductor layer include a same material as each other.

Assignees

• Samsung Display Co Ltd

Inventors

• Yoon Juwon
• Yang Taehoon

Classifications

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title