Three-dimensional semiconductor memory devices having a vertical semiconductor pattern

Patent metadata

Field	Value
Publication number	US-11839084-B2
Application number	US-202217825619-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	Apr 30, 2018
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device comprising:
a horizontal semiconductor layer;
a source structure on the horizontal semiconductor layer, the source structure comprising a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer;
an electrode structure comprising a plurality of electrodes vertically stacked on the source structure; and
a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure,
wherein the first source conductive pattern has a first thickness in a vertical direction perpendicular to a top surface of the horizontal semiconductor layer,
the second source conductive pattern has a second thickness in the vertical direction, and
the second thickness is different from the first thickness.

2. The 3D semiconductor memory device of claim 1 ,
wherein the horizontal semiconductor layer has a third thickness in the vertical direction, and
wherein the third thickness is different from the first thickness and the second thickness.

3. The 3D semiconductor memory device of claim 1 , further comprising:
a source plug penetrating the electrode structure and the source structure and spaced apart from the vertical semiconductor pattern; and
an insulating spacer disposed between the source plug and the electrode structure,
wherein a bottom surface of the source plug is located at a higher level than a bottom surface of the vertical semiconductor pattern.

4. The 3D semiconductor memory device of claim 1 , further comprises:
a source plug penetrating the electrode structure and the source structure and spaced apart from the vertical semiconductor pattern; and
an insulating spacer disposed between the source plug and the electrode structure,
wherein the source plug includes a discontinuous interface extending in the vertical direction.

5. The 3D semiconductor memory device of claim 1 ,
wherein the first source conductive pattern includes a discontinuous interface at a level between the top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

6. The 3D semiconductor memory device of claim 1 ,
wherein the first source conductive pattern comprises:
a horizontal portion extending in parallel to the electrode structure under the electrode structure; and
a sidewall portion extending from the horizontal portion in the vertical direction and surrounding the portion of the sidewall of the vertical semiconductor pattern, and
wherein the horizontal portion of the first source conductive pattern has the first thickness.

7. The 3D semiconductor memory device of claim 6 ,
wherein a top surface of the sidewall portion is located at a level between a bottom surface of a lowermost one of the electrodes and a top surface of the first source conductive pattern, and
wherein a bottom surface of the sidewall portion is located at a level between a bottom surface of the vertical semiconductor pattern and the top surface of the horizontal semiconductor layer.

8. The 3D semiconductor memory device of claim 1 ,
wherein the first source conductive pattern comprises:
a lower portion adjacent to the top surface of the horizontal semiconductor layer; and
an upper portion adjacent to a bottom surface of the second source conductive pattern, and
wherein the upper portion and the lower portion have different crystal structures from each other.

9. The 3D semiconductor memory device of claim 1 ,
wherein the first and second source conductive patterns include a semiconductor material doped with impurities having a first conductivity type, and
wherein a concentration of the impurities in the first source conductive pattern is greater than a concentration of the impurities in the second source conductive pattern.

10. The 3D semiconductor memory device of claim 1 , further comprising:
a data storage pattern vertically extending between the vertical semiconductor pattern and the electrode structure; and
a dummy data storage pattern vertically spaced apart from the data storage pattern and disposed between the vertical semiconductor pattern and the horizontal semiconductor layer,
wherein a bottom surface of the data storage pattern is in contact with a portion of the first source conductive pattern.

11. The 3D semiconductor memory device of claim 10 ,
wherein the bottom surface of the data storage pattern is located at a level between a bottom surface of a lowermost one of the electrodes and a bottom surface of the second source conductive pattern.

12. A three-dimensional (3D) semiconductor memory device comprising:
a source structure on a horizontal semiconductor layer, the source structure comprising a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer;
an electrode structure comprising a plurality of electrodes vertically stacked on the source structure; and
a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure,
wherein the first source conductive pattern has a first thickness in a vertical direction perpendicular to a top surface of the horizontal semiconductor layer,
the second source conductive pattern has a second thickness in the vertical direction, and
the first thickness is greater than the second thickness.

13. The 3D semiconductor memory device of claim 12 ,
wherein the horizontal semiconductor layer has a third thickness in the vertical direction, and
wherein the third thickness is greater than the first thickness.

14. The 3D semiconductor memory device of claim 12 ,
wherein the first source conductive pattern comprises:
a horizontal portion extending in parallel to the electrode structure and disposed between the second source conductive pattern and the horizontal semiconductor layer; and
a sidewall portion extending from the horizontal portion in the vertical direction and surrounding the portion of the sidewall of the vertical semiconductor pattern, and
wherein the horizontal portion of the first source conductive pattern has the first thickness.

15. The 3D semiconductor memory device of claim 12 , further comprises:
a source plug penetrating the electrode structure and the source structure and spaced apart from the vertical semiconductor pattern; and
an insulating spacer disposed between the source plug and the electrode structure,
wherein a bottom surface of the source plug is located at a higher level than a bottom surface of the vertical semiconductor pattern.

16. The 3D semiconductor memory device of claim 15 ,
wherein the source plug comprises a lower portion adjacent to the source structure and an upper portion adjacent to the electrode structure, and
wherein the upper portion of the source plug includes a discontinuous interface extending in the vertical direction.

17. The 3D semiconductor memory device of claim 12 , further comprising:
a data storage pattern vertically extending between the vertical semiconductor pattern and the electrode structure; and
a dummy data storage pattern vertically spaced apart from the data storage pattern and disposed between the vertical semiconductor pattern and the horizontal semiconductor layer,
wherein a bottom surface of

Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Shin Joongshik
• Yun Jihye

Classifications

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/43

  Layouts of interconnections · CPC title