Semiconductor processing system with in-situ electrical bias and methods thereof

Patent metadata

Field	Value
Publication number	US-11837652-B2
Application number	US-202217662579-A
Country	US
Kind code	B2
Filing date	May 9, 2022
Priority date	Apr 6, 2020
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

First claim

What is claimed is:

1. A system for processing semiconductor wafers, the system comprising:
a processing chamber;
a substrate holder configured to support a semiconductor wafer;
a heating element configured to heat the semiconductor wafer supported by the substrate holder;
a first electrode configured to be detachably attached to a first major surface of the semiconductor wafer;
a first wire coupling the first electrode to a first potential node; and
a load-rail configured to detachably attach the first electrode to the first major surface of the semiconductor wafer and load the semiconductor wafer into the processing chamber.

2. The system of claim 1 , further comprising:
a second electrode coupled to the substrate holder; and
a second wire coupling the second electrode to a second potential node.

3. The system of claim 2 , further comprising:
a third electrode configured to be detachably attached to the first major surface of the semiconductor wafer;
a voltage monitoring meter; and
a third wire coupling the third electrode to the voltage monitoring meter.

4. The system of claim 1 , further comprising:
a second electrode configured to be detachably attached to a second major surface of the semiconductor wafer; and
a second wire coupling the second electrode to a second potential node.

5. The system of claim 1 , further comprising:
a power supply coupled to the first potential node.

6. The system of claim 1 , wherein the first electrode comprises a tungsten ribbon and the first wire comprises a tungsten wire.

7. A system for processing semiconductor wafers, the system comprising:
a processing chamber;
a substrate holder configured to support a plurality of semiconductor wafers in the processing chamber;
a heating element configured to heat the plurality of semiconductor wafers supported by the substrate holder;
a first electrode configured to be detachably attached to a first major surface of a semiconductor wafer of the plurality of semiconductor wafers;
a first wire coupling the first electrode to a first potential node;
a first bus comprising a first plurality of electrodes configured to contact a first side of each of the plurality of semiconductor wafers; and
a second bus comprising a second plurality of electrodes configured to contact a second side of each of the plurality of semiconductor wafers.

8. The system of claim 7 , wherein the heating element is placed inside the processing chamber.

9. The system of claim 7 , wherein the heating element is placed outside the processing chamber.

10. The system of claim 7 , wherein the substrate holder comprises a plurality of slots for holding the plurality of semiconductor wafers horizontally over each other.

11. The system of claim 7 , wherein the substrate holder comprises a supporting plate configured to support the plurality of semiconductor wafers.

12. The system of claim 11 , wherein the supporting plate comprises a conductive material configured to be coupled to a reference potential node.

13. The system of claim 11 , wherein the supporting plate comprises a ring shape.

14. The system of claim 7 , further comprising a load rail stage configured to position the plurality of semiconductor wafers in the substrate holder, and into a heating zone of the processing chamber.

15. A system for processing semiconductor wafers, the system comprising:
a processing chamber;
a substrate holder configured to support a plurality of semiconductor wafers in the processing chamber;
a heating element configured to heat the plurality of semiconductor wafers supported by the substrate holder;
a first bus comprising a first plurality of electrodes coupled to a first potential node and configured to be detachably attached to a first major surface of each of the plurality of semiconductor wafers;
a second bus comprising a second plurality of electrodes coupled to a second potential node and configured to be detachably attached to a second major surface of each of the plurality of semiconductor wafers; and
a load rail stage configured to position the plurality of semiconductor wafers in the substrate holder into a heating zone of the processing chamber.

16. The system of claim 15 , wherein the heating element is placed inside the processing chamber.

17. The system of claim 15 , wherein the heating element is placed outside the processing chamber.

18. The system of claim 15 , wherein the substrate holder comprises a plurality of slots for holding the plurality of semiconductor wafers horizontally over each other.

19. The system of claim 15 , wherein the substrate holder comprises a supporting plate configured to support the plurality of semiconductor wafers, the supporting plate comprising a ring shape.

20. The system of claim 15 , further comprising:
a voltage monitoring meter coupled to the first bus.

Assignees

• Tokyo Electron Ltd

Inventors

• Hurley David
• Domsa Ioan
• Colgan Ian
• Van Der Linde Gerhardus
• Hughes Patrick
• Burel Maciej
• Clarke Barry
• Popovici Mihaela Ioana
• Ragnarsson Lars-Ake

Classifications

• H10P72/0431

  Apparatus for thermal treatment · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P72/0602

  Temperature monitoring · CPC title