Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact

Patent metadata

Field	Value
Publication number	US-11837641-B2
Application number	US-201916719281-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Dec 18, 2019
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising: a conductive via above a semiconductor substrate, the conductive via comprising a metal-containing material; a vertical arrangement of horizontal nanowires above a fin protruding from the semiconductor substrate, a channel region of the vertical arrangement of horizontal nanowires electrically isolated from the fin, wherein the fin is in direct contact with the metal-containing material of the conductive via; and a gate stack over the vertical arrangement of horizontal nanowires.

2. The integrated circuit structure of claim 1 , further comprising a second conductive via on the semiconductor substrate, the second conductive via laterally adjacent to the conductive via.

3. The integrated circuit structure of claim 1 , further comprising:
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.

4. The integrated circuit structure of claim 3 , further comprising:
a pair of conductive contacts on the pair of epitaxial source or drain structures.

5. The integrated circuit structure of claim 4 , wherein one of the pair of conductive contacts is electrically connected to the conductive via.

6. The integrated circuit structure of claim 3 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.

7. The integrated circuit structure of claim 3 , wherein the pair of epitaxial source or drain structures is a pair of discrete epitaxial source or drain structures.

8. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

9. An integrated circuit structure, comprising: a vertical arrangement of horizontal nanowires above a fin protruding from a semiconductor substrate, a channel region of the vertical arrangement of horizontal nanowires electrically isolated from the fin; a gate stack over the vertical arrangement of horizontal nanowires; a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires; and a pair of conductive contacts on corresponding ones of the pair of epitaxial source or drain structures, one but not both of the pair of conductive contacts comprising a metal-containing material in direct contact with the fin.

10. The integrated circuit structure of claim 9 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.

11. The integrated circuit structure of claim 9 , wherein the pair of epitaxial source or drain structures is a pair of discrete epitaxial source or drain structures.

12. The integrated circuit structure of claim 9 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

13. The integrated circuit structure of claim 9 , wherein the vertical arrangement of horizontal nanowires is a vertical arrangement of horizontal silicon nanowires.

14. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a conductive via above a semiconductor substrate, the conductive via comprising a metal-containing material; a vertical arrangement of horizontal nanowires above a fin protruding from the semiconductor substrate, a channel region of the vertical arrangement of horizontal nanowires electrically isolated from the fin, wherein the fin is in direct contact with the metal-containing material of the conductive via; and a gate stack over the vertical arrangement of horizontal nanowires.

15. The computing device of claim 14 , further comprising:
a memory coupled to the board.

16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.

17. The computing device of claim 14 , wherein the component is a packaged integrated circuit die.

18. The computing device of claim 14 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Guha Biswajeet
• Hsu William
• Lin Chung-Hsun
• Phoa Kinyip
• Golonzka Oleg
• Ghani Tahir
• Kolluru Kalyan
• Jack Nathan
• THOMSON Nicholas
• Kar Ayan
• Orr Benjamin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title

• H10D64/01

  Manufacture or treatment · CPC title