Coated semiconductor dies

Patent metadata

Field	Value
Publication number	US-11837518-B2
Application number	US-202017003382-A
Country	US
Kind code	B2
Filing date	Aug 26, 2020
Priority date	Aug 26, 2020
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

First claim

What is claimed is:

1. A chip scale package (CSP), comprising:
a semiconductor die;
a conductive terminal coupled to the semiconductor die; and
a non-conductive coat including a top portion covering a backside of the semiconductor die and a sidewall portion covering a sidewall of the semiconductor die, the non-conductive coat having a thickness of less than 45 microns, the sidewall portion of the non-conductive coat having a uniform thickness on the sidewall of the semiconductor die and the top portion having a width corresponding to a sum of a width of the semiconductor die and twice of the uniform thickness of the sidewall portion, wherein a strip of the sidewall of the semiconductor die is exposed and the sidewall portion terminates at the strip of the sidewall, wherein the strip of the sidewall abuts a frontside of the semiconductor die opposite the backside.

2. The CSP of claim 1 , wherein the CSP comprises a wafer level CSP (WCSP).

3. The CSP of claim 1 , wherein the non-conductive coat comprises an epoxy.

4. The CSP of claim 1 , wherein the uniform thickness of the sidewall portion of the non-conductive coat ranges from 2 microns to 6 microns.

5. The CSP of claim 1 , wherein the non-conductive coat is to block at least one type of light from entering the semiconductor die.

6. The CSP of claim 1 , wherein the non-conductive coat abuts the backside of the semiconductor die and four sidewalls of the semiconductor die.

7. The CSP of claim 1 , wherein the non-conductive coat abuts the backside of the semiconductor die and at least some, but not all, of each of four sidewalls of the semiconductor die.

8. A package, comprising:
a semiconductor die;
a conductive terminal coupled to a first surface of the semiconductor die; and
a non-conductive coat including a first portion covering a second surface of the semiconductor die opposite the first surface and a second portion covering a sidewall of the semiconductor die, the second portion of the non-conductive coat having a uniform thickness on the sidewall of the semiconductor die and the first portion having a width corresponding to a sum of a width of the semiconductor die and twice of the uniform thickness of the second portion, wherein a strip of the sidewall of the semiconductor die is exposed and the second portion terminates at the strip of the sidewall, and wherein the strip of the sidewall abuts the first surface.

9. The package of claim 8 , wherein the uniform thickness is a second uniform thickness, and wherein the first portion of the non-conductive coat has a first uniform thickness on the second surface of the semiconductor die.

10. The package of claim 9 , wherein the first uniform thickness on the second surface of the semiconductor die is same as the second uniform thickness of the sidewall of the semiconductor die.

11. The package of claim 8 , wherein the non-conductive coat abuts the second surface of the semiconductor die and at least some, but not all, of each of four sidewalls of the semiconductor die.

12. The package of claim 8 , wherein the non-conductive coat comprises at least one of epoxy, resin, paint, tape, mold compound, or laminate.

13. A package, comprising:
a semiconductor die including a backside and a frontside opposite the backside; and
a non-conductive coat including a first portion covering the backside of the semiconductor die and a second portion covering a sidewall of the semiconductor die, the first portion having a first uniform thickness and the second portion having a second uniform thickness, wherein
the first portion has a width corresponding to a sum of a width of the semiconductor die and twice of the second uniform thickness; and
a strip of the sidewall of the semiconductor die is exposed and the second portion terminates at the strip of the sidewall, wherein the strip of the sidewall abuts the frontside.

14. The package of claim 13 , wherein the semiconductor die includes optical circuitry.

15. The package of claim 14 , further comprising:
a conductive terminal coupled to the frontside of the semiconductor die, wherein the conductive terminal is coupled to the optical circuitry.

16. The package of claim 13 , wherein the first uniform thickness is same as the second uniform thickness.

17. The package of claim 13 , wherein the strip of the sidewall has a width ranging from 10 microns to 15 microns.

18. The package of claim 13 , wherein the non-conductive coat is exclusive of filler particles.

19. The package of claim 13 , wherein the non-conductive coat is configured to block at least one type of light from entering the semiconductor die.

Assignees

• Texas Instruments Inc

Inventors

• Wyant Michael Todd
• Sherbin Matthew John
• Manack Christopher Daniel
• Thompson Patrick Francis
• How You Chye

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title