Memory device for correcting pulse duty and memory system including the same

Patent metadata

Field	Value
Publication number	US-11837310-B2
Application number	US-202217569144-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Aug 20, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including a plurality of memory blocks and a primary pulse correction module; and
a controller configured to transmit a control signal for controlling the memory device,
wherein the primary pulse correction module includes:
a reset signal generation circuit configured to generate a reset signal on the basis of the control signal;
a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal; and
a corrected primary pulse output circuit configured to correct a duty ratio of the primary pulse of the control signal to be outputted by adjusting a rising edge of the detection signal after the end of a preamble period of the control signal.

2. The memory system according to claim 1 , wherein the control signal is one of a data strobe signal and a read enable signal.

3. The memory system according to claim 2 , wherein the reset signal generation circuit is further configured to change a logic level of the reset signal when the preamble period of the control signal starts.

4. The memory system according to claim 3 , wherein the reset signal generation circuit comprises a plurality of NAND gates, a plurality of inverters and at least one flip-flop.

5. The memory system according to claim 2 , wherein the primary pulse detection circuit outputs the detection signal by detecting that the preamble period of the control signal ends and a logic level of the control signal is changed from a logic low level to a logic high level.

6. The memory system according to claim 5 , wherein the primary pulse detection circuit comprises at least one NAND gate, at least one inverter and at least one flip-flop.

7. The memory system according to claim 5 , wherein the detection signal comprises a first detection signal and a second detection signal which is an inverted signal of the first detection signal.

8. The memory system according to claim 7 , wherein:
the control signal comprises a first control signal and a second control signal which is an inverted signal of the first control signal, and
the corrected primary pulse output circuit includes:
a first corrected primary pulse output circuit configured to output a first corrected primary pulse by correcting a duty ratio of a primary pulse of the first control signal on the basis of the first control signal and the first detection signal; and
a second corrected primary pulse output circuit configured to output a second corrected primary pulse by correcting a duty ratio of a primary pulse of the second control signal on the basis of the second control signal and the second detection signal.

9. The memory system according to claim 8 , wherein:
the first corrected primary pulse output circuit includes:
a first PMOS transistor and a first NMOS transistor both configured to receive the first control signal;
a second PMOS transistor configured to receive a first duty correction signal; and
a second NMOS transistor configured to receive a second duty correction signal, and
wherein the second corrected primary pulse output circuit includes:
a third PMOS transistor and a third NMOS transistor both configured to receive the second control signal;
a fourth PMOS transistor configured to receive a third duty correction signal; and
a fourth NMOS transistor configured to receive a fourth duty correction signal.

10. The memory system according to claim 6 , wherein the primary pulse detection circuit further comprises an OR gate which outputs a signal to a reset signal input terminal of the flip-flop by performing an OR logic operation on the chip enable signal and a signal outputted by the reset signal generation circuit.

11. A memory device comprising:
a reset signal generation circuit configured to generate a reset signal on the basis of a control signal;
a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal; and
a corrected primary pulse output circuit configured to correct a duty ratio of the primary pulse of the control signal to be outputted by adjusting a rising edge of the detection signal after end of a preamble period of the control signal.

12. The memory device according to claim 11 , wherein the control signal is one of a data strobe signal and a read enable signal.

13. The memory device according to claim 12 , wherein the reset signal generation circuit is further configured to change a logic level of the reset signal when the preamble period of the control signal starts.

14. The memory device according to claim 13 , wherein the reset signal generation circuit comprises a plurality of NAND gates, a plurality of inverters and at least one flip-flop.

15. The memory device according to claim 12 , wherein the primary pulse detection circuit outputs the detection signal by detecting that the preamble period of the control signal ends and a logic level of the control signal is changed from a logic low level to a logic high level.

16. The memory device according to claim 15 , wherein the primary pulse detection circuit comprises at least one NAND gate, at least one inverter and at least one flip-flop.

17. The memory device according to claim 15 , wherein the detection signal comprises a first detection signal and a second detection signal which is an inverted signal of the first detection signal.

18. The memory device according to claim 17 , wherein:
the control signal comprises a first control signal and a second control signal which is an inverted signal of the first control signal, and
the corrected primary pulse output circuit includes:
a first corrected primary pulse output circuit configured to output a first corrected primary pulse by correcting a duty ratio of a primary pulse of the first control signal on the basis of the first control signal and the first detection signal; and
a second corrected primary pulse output circuit configured to output a second corrected primary pulse by correcting a duty ratio of a primary pulse of the second control signal on the basis of the second control signal and the second detection signal.

19. The memory device according to claim 18 , wherein:
the first corrected primary pulse output circuit includes:
a first PMOS transistor and a first NMOS transistor both configured to receive the first control signal;
a second PMOS transistor configured to receive a first duty correction signal; and
a second NMOS transistor configured to receive a second duty correction signal, and
wherein the second corrected primary pulse output circuit includes:
a third PMOS transistor and a third NMOS transistor both configured to receive the second control signal;
a fourth PMOS transistor configured to receive a third duty correction signal; and
a fourth NMOS transistor configured to receive a fourth duty correction signal.

20. An operating method of a memory device, the operating method comprising:
determining whether a command latch enable signal and a chip enable signal are changed from logic high levels to logic low levels;
detecting a pulse and subsequent pulses of a data strobe signal or a read enable signal immediately after an end of a preamble section of the data strobe signal, when the command latch enable signal and the chip enable signal are changed from the logic high levels to the logic low levels; and
maintaining a reset state when the command latch enable signal

Assignees

• Sk Hynix Inc

Inventors

• Hong Jaehyeong
• Kong In Seok
• Kim Gwan Woo
• Park Jae Young
• Shon Kwan Su
• An Soon Sung
• Yang Daeho
• Ok Sung Hwa
• Jang Junseo
• Jeong Yo Han
• Choi Eun Ji

Classifications

• G11C29/4401 Primary

  for self repair · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/15066

  using bistable devices (H03K5/15093 takes precedence) · CPC title

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title