Nonvolatile memory device for performing duty correction operation, memory system, and operating method thereof

Patent metadata

Field	Value
Publication number	US-2017053684-A1
Application number	US-201514981446-A
Country	US
Kind code	A1
Filing date	Dec 28, 2015
Priority date	Aug 20, 2015
Publication date	Feb 23, 2017
Grant date	—

Abstract

A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation and a read operation in response to a ZQ calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.

First claim

1 . A memory system comprising:
a memory controller; and a nonvolatile memory device suitable for performing a specified operation in response to a command inputted from the memory controller; wherein the nonvolatile memory device sequentially performs a ZQ calibration operation for impedance matching of a signal line between the memory controller and the nonvolatile memory device and a read operation in response to a ZQ calibration enable signal and a read enable signal inputted from the memory controller; wherein during a ZQ calibration operation period, the memory controller outputs the read enable signal to the nonvolatile memory device, and the nonvolatile memory device performs a duty correction operation in response to the read enable signal and sets a duty ratio; and wherein during a read operation period, the nonvolatile memory device generates an internal clock signal based on the set duty ratio, and outputs data in synchronization with the internal clock signal.

2 . The memory system according to claim 1 , wherein the nonvolatile memory device comprises:
a duty ratio control block suitable for receiving the read enable signal, performing the duty correction operation and setting the duty ratio, during the ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, during a read operation period; a clock generation block suitable for generating the internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.

3 . The memory system according to claim 2 , wherein the duty ratio control block comprises:
a delay line unit suitable for delaying the read enable signal by a preset time in response to a delay line control signal, and outputting a delayed clock; a duty ratio detection unit suitable for detecting a duty ratio of the delayed clock and outputting detection signals, during the ZQ calibration operation period; a delay line control unit suitable for outputting the delay line control signal in response to the detection signals; and an output driver suitable for outputting the delayed clock as the duty-corrected clock during a read operation period.

4 . The memory system according to claim 1 , wherein the nonvolatile memory device comprises:
a duty ratio control block suitable for receiving the read enable signal and the internal clock signal, performing the duty correction operation and setting the duty ratio, in the ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, during a read operation period; a clock generation block suitable for generating the internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.

5 . The memory system according to claim 4 , wherein the duty ratio control block comprises:
a signal selection unit suitable for selecting and outputting the read enable signal or the internal clock signal in response to a select signal which defines an initial period of the ZQ calibration operation period; a delay line unit suitable for delaying an output signal of the signal selection unit by a preset time in response to a delay line control signal, and outputting a delayed clock; a duty ratio detection unit suitable for detecting a duty ratio of the delayed clock and outputting detection signals, in the ZQ calibration operation period; a delay line control unit suitable for outputting the delay line control signal in response to the detection signals; and an output driver suitable for outputting the delayed clock as the duty-corrected clock during a read operation period and the ZQ calibration operation period.

6 . The memory system according to claim 5 ,
wherein the select signal is enabled in a remaining period, following the initial period, of the ZQ calibration operation period, and wherein the signal selection unit selects the internal clock signal when the select signal is enabled, and selects the read enable signal when the select signal is disabled.

7 . The memory system according to claim 1 , wherein the nonvolatile memory device comprises:
a frequency detection block suitable for receiving the read enable signal, detecting a frequency of the memory system and outputting a duty correction enable signal, during the ZQ calibration operation period; a duty ratio control block suitable for receiving the read enable signal and the internal clock signal, performing the duty correction operation and setting the duty ratio, in response to the duty correction enable signal, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, during a read operation period; a low-speed operation determination block suitable for being disabled in response to the duty correction enable signal, and receiving the read enable signal and outputting an internal read enable signal; a clock generation block suitable for generating the internal clock signal in response to the duty-corrected clock or the internal read enable signal; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.

8 . The memory system according to claim 7 , wherein the frequency detection block enables the duty correction enable signal when the frequency of the memory system is a high frequency, and disables the duty correction enable signal when the frequency of the memory system is a low frequency.

9 . The memory system according to claim 7 , wherein the clock generation block selects the duty-corrected clock when the duty correction enable signal is enabled, and selects the internal read enable signal when the duty correction enable signal is disabled.

10 . The memory system according to claim 7 , wherein the frequency detection block comprises:
a frequency division unit suitable for dividing a frequency of the read enable signal which is inputted in the ZQ calibration operation period, by a preset number, and outputting a frequency-divided clock signal; a code detection unit suitable for receiving the frequency-divided clock signal, detecting a level of the frequency-divided clock signal at a preset number of times, and outputting a plurality of digital codes; and a duty correction enable signal output unit suitable for determining and outputting whether to enable the duty correction enable signal, based on the plurality of digital codes.

11 . The memory system according to claim 10 ,
wherein the code detection unit comprises a plurality of time delay circuits which are coupled in series with each other, and wherein each time delay circuit comprises: a plurality of unit delay sections coupled in series, suitable for delaying signals inputted thereto, by a unit time, and outputting resultant signals; and a plurality of comparison sections suitable for comparing outputs of the corresponding unit delay sections with a phase of the frequency-divided clock signal, and outputting comparison results as corresponding digital codes.

12 . The memory system according to claim 1 , wherein, in the ZQ calibration operation period, the read enable signal toggles during an enable period of the ZQ calibration enable signal.

13 . A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation for impedance matching of a

Assignees

• Sk Hynix Inc

Inventors

• Choi Hoon

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/32

  Timing circuits · CPC title