Non-volatile memory with adjusted bit line voltage during verify

Patent metadata

Field	Value
Publication number	US-11837296-B2
Application number	US-202117505179-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Oct 19, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

First claim

What is claimed is:

1. A non-volatile storage apparatus, comprising:
a plurality of word lines, including a selected word line;
non-volatile memory cells connected to the selected word line; and
a control circuit connected to the non-volatile memory cells, the control circuit is configured to apply a programming signal to a plurality of the non-volatile memory cells via the selected word line in order to program the plurality of the non-volatile memory cells to a set of data states, the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells including applying bit line voltages during program verification based on word line position of the selected word line and data state being verified such that for a same word line position of the selected word line two different bit line voltages will be applied for two different data states being verified.

2. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the programming signal by applying doses of the programming signal to the plurality of the non-volatile memory cells; and
the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells by applying bit line voltages between the doses of the programming signal based on word line position of the selected word line zone and data state being verified.

3. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the programming signal by applying voltage pulses to the plurality of the non-volatile memory cells; and
the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells by applying bit line voltages between the voltage pulses based on word line position of the selected word line and data state being verified.

4. The non-volatile storage apparatus of claim 1 , further comprising:
a plurality of bit lines connected to the non-volatile memory cells, the plurality of word lines being divided into word line zones, the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells including applying bit line voltages during program verification based on word line zone of the selected word line and data state being verified.

5. The non-volatile storage apparatus of claim 4 , wherein:
the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells including applying bit line voltages during program verification based on word line zone of the selected word line and data state being verified by using bit line voltage offsets from a nominal bit line voltage, different word line zones have different bit line voltage offsets, different data states being verified have different bit line voltage offsets.

6. The non-volatile storage apparatus of claim 5 , wherein:
the bit line offsets based on word line zones are configurable; and
the control circuit is configured to check configuration information to determine magnitude of the bit line offsets based on word line zones.

7. The non-volatile storage apparatus of claim 1 , further comprising:
a plurality of bit lines connected to the non-volatile memory cells, the plurality of word lines being divided into word line zones, the control circuit includes a plurality of sense amplifiers connected to the bit lines, the sense amplifiers each include a bit line clamp transistor that maintains a constant voltage on a respective connected bit line, the control circuit is configured to program the non-volatile memory cells by applying a series of voltage pulses to the selected word line, the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells including applying a reference voltage to the selected word line and applying gate voltages to the bit line clamp transistors based on word line zone of the selected word line and a data state being verified.

8. The non-volatile storage apparatus of claim 1 , further comprising:
a plurality of bit lines connected to the non-volatile memory cells the plurality of word lines being divided into word line zones based on distance to the bit lines, the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells including applying bit line voltages during program verification based on word line zone of the selected word line and data state being verified.

9. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the programming signal by applying voltage pulses to the plurality of the non-volatile memory cells; and
the control circuit is configured to perform program verification for the plurality of the non-volatile memory cells by applying bit line voltages between the voltage pulses based on word line position of the selected word line and a set of data states being verified between a particular set of the voltage pulses.

10. The non-volatile storage apparatus of claim 9 , wherein:
all memory cells being verified between the particular set of the voltage pulses receive the same bit line voltage.

11. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the programming signal by applying voltage pulses to the plurality of the non-volatile memory cells; and
memory cells being verified for different data states between a particular set of the voltage pulses receive different bit line voltages during program verification.

12. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory cells are positioned on a first semiconductor die; and
the control circuit is positioned on a second semiconductor die that is directly bonded to the first semiconductor die.

13. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory cells comprise multiple vertical NAND strings, each non-volatile memory cell of the plurality of the non-volatile memory cells is on a separate NAND string of the multiple vertical NAND strings and is connected to a common word line.

14. A non-volatile storage apparatus, comprising:
a non-volatile memory structure that includes a plurality of non-volatile memory cells, a plurality of bit lines connected to the non-volatile memory cells and a plurality of word lines connected to the non-volatile memory cells, the word lines being divided into word line zones based on distance to the bit lines; and
a control circuit connected to the non-volatile memory structure, the control circuit includes a plurality of sense amplifiers connected to the bit lines, the sense amplifiers each include a bit line clamp transistor that maintains a constant voltage on a respective connected bit line, the control circuit is configured to program the non-volatile memory cells by applying a series of voltage pulses to a selected word line, the control circuit is configured to verify programming of the non-volatile memory cells by applying a reference voltage to the selected word line and applying gate voltages to the bit line clamp transistors based on the selected word line's word line zone and data state being verified such that for a same word line zone different gate voltages will be applied for different data states being verified.

15. The non-volatile storage apparatus of claim 14 , wherein:
the sense amplifiers each include a bit line isolation transistor that is connected between respective bit lines and bit line clamp transistors, the bit line isola

Assignees

• Sandisk Technologies Llc

Inventors

• Lien Yu-Chung
• Yuan Jiahui
• Kwon Ohwon

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title