Sequential write and sequential write verify in memory device

Patent metadata

Field	Value
Publication number	US-9881674-B2
Application number	US-201414581631-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 11, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

First claim

What is claimed is:

1. A method comprising:
performing a first stage of an operation of storing information in a first memory cell and a second memory cell, the first memory cell included in a first memory cell string, the first memory string electrically connected to a data line during the first stage through a first select transistor, the second memory cell included in a second memory cell string, the second memory cell string electrically connected to the data line during the first stage through a second select transistor, and first and second memory cells sharing an access line; and
performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state.

2. The method of claim 1 , wherein performing the first stage of the operation includes changing a state of each of the first and second memory cells before the second stage is performed.

3. The method of claim 2 , wherein the state of each of the first and second memory cells includes an erase state before the second stage is performed.

4. The method of claim 1 , wherein performing the second stage of the operation includes:
applying a program verify voltage during a first time interval of the second stage and a second time interval of the second stage to the access line;
keeping a value of the program verify voltage unchanged between the first time interval and the second time interval;
determining, during the first time interval, whether the first memory cell reaches the target state; and
determining, during the second time interval, whether the second memory cell reach the target state.

5. The method of claim 1 , wherein performing a second stage of the operation includes:
passing a signal from the data line to a first page buffer electrically connected to the data line during a time interval of the second stage to determine whether the first memory cell reaches the target state based on information provided by the signal to the first page buffer; and
passing the signal from the data line to a second page buffer electrically connected to the data line during another time interval of the second stage to determine whether the second memory cell reaches the target state based on information provided by the signal to the second page buffer.

6. The method of claim 1 , wherein each of the first and second memory cells is configured as a single level cell, and the target state corresponds to a value of a single bit of data.

7. The method of claim 1 , wherein each of the first and second memory cells is configured as a multi-level cell, and the target state corresponds to a value of one bit among the multiple bits to be stored in each of the first and second memory cells.

8. A method comprising:
changing a value of a threshold voltage of a first memory cell during a write operation of a device, the first memory cell included in a first memory cell string, the first memory string electrically connected to a data line during the write operation through a first select transistor;
changing a value of a threshold voltage of a second memory cell during the write operation after the changing of the value of the threshold voltage the first memory cell, the second memory cell included in a second memory cell string, the second memory cell string electrically connected to the data line during the write operation through a second select transistor, and first and second memory cells sharing an access line; and
determining whether each of the first and second memory cells reaches a target threshold voltage after the changing of the value of the threshold voltage of the second memory cell.

9. The method of claim 8 , wherein changing the value of the threshold voltage of the first memory cell includes applying a first programming voltage to the access line, and changing the value of the threshold voltage of the second memory cell includes applying a second programming voltage to the access line, wherein first and second voltages have a same value.

10. The method of claim 8 , wherein changing the value of the threshold voltage of each of the first and second memory cells includes increasing the values of the threshold voltages of the first and second memory cells.

11. The method of claim 8 , wherein changing the value of the threshold voltage of each of the first and second memory cells includes:
causing the value of the threshold voltage of the first memory cell to change from a negative value to a positive value; and
causing the value of the threshold voltage of the second memory cell to change from a negative value to a positive value.

12. The method of claim 8 , wherein the first stage includes a write stage of the operation and the second stage includes a write verify stage of the operation.

13. A method comprising:
applying a first voltage to an access line during a first time interval of an operation to program a first memory cell, the first memory cell included in a first memory cell, the first memory string electrically connected to a data line during the operation through a first select transistor;
applying the first voltage to the access line during a second time interval of the operation to program a second memory cell, the second memory cell included in a second memory cell string, the second memory cell string electrically connected to the data line during the operation through a second select transistor, first and second memory cells sharing the access line; and
applying a second voltage to the access line during a third time interval and a fourth time interval of the operation to determine whether the first and second memory cells reach a target threshold voltage, without applying another voltage to the access line during a time interval between the third and fourth time intervals.

14. The method of claim 13 , further comprising:
applying a third voltage to the access line during a time interval between the first and second the time intervals, wherein a value of the third voltage is less than a value of the first voltage.

15. The method of claim 14 , wherein the value of the third voltage is zero.

16. The method of claim 14 , wherein the value of the third voltage is greater than zero.

17. The method of claim 13 , further comprising:
electrically connecting the data line to a first page buffer during the third time interval to determine whether the threshold voltage of the first memory cell reaches the target threshold voltage based on information provided from the data line to the first page buffer during the third time interval; and
electrically connecting the data line to a second page buffer during the fourth time interval to determine whether the threshold voltage of the second memory cell reaches the target threshold voltage based on information provided from the data line to the second page buffer during the fourth time interval.

18. An apparatus comprising:
a data line;
a first memory cell included in a first memory cell string;
a second memory cell included in a second memory cell string;
a first select transistor to electrically connect the first memory cell string to the data line;
a second select transistor to electrically connect the second memory cell string to the data line;
an access line shared by the first and second memory cells; and
a module to perform a write stage of a write operation of storing information in the first and second memory cells, and to perform a write verify stage of the write operation after the write stage to determine whether each of the first and second memory

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title