Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9449708-B2
Application number	US-201314138314-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Sep 9, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array configured having NAND strings arranged therein; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to apply a verify voltage to a selected word line, apply a read pass voltage that renders conductive an unselected memory cell regardless of cell data to an unselected word line, and apply a bit line voltage of a certain value to a selected bit line, thereby executing a write verify operation that determines whether a selected memory cell has a desired threshold voltage or not. The control circuit is configured capable of changing a voltage value of the bit line voltage based on a position of the selected word line among the plurality of word lines relative to the NAND string.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array configured to have NAND strings arranged therein, each of the NAND strings including: a memory string configured to have a plurality of memory cells connected in series therein; and a first select transistor and a second select transistor respectively connected to two ends of the memory string;
a plurality of word lines respectively connected to control gate electrodes of the plural…

Assignees

• Toshiba Kk

Inventors

• Hirai Ryota
• Shiino Yasuhiro

Classifications

• G11C16/3427

  Physics · mapped topic

• G11C16/0483

  Physics · mapped topic

• G11C16/3459 Primary

  Physics · mapped topic