Data storage device with data verification circuitry

Patent metadata

Field	Value
Publication number	US-11836035-B2
Application number	US-202117396199-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Aug 6, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

First claim

What is claimed is:

1. A data storage device, comprising:
a non-volatile memory device including a controller;
a memory block including a plurality of memory dies; and
a data verification circuit configured to:
receive a memory access command from the controller,
perform a memory access operation based on the memory access command,
determine a number of bytes that is transferred during the memory access operation,
determine whether the number of transferred bytes is equal to a predetermined number of bytes,
in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes, append a second number of additional bytes to the transferred bytes, wherein the second number of additional bytes is equal to a difference between the predetermined number of bytes and the number of transferred bytes, and
in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes, set a transfer status fail bit indicating that the number of transferred bytes is not equal to the predetermined number of bytes,
wherein the second number of additional bytes are randomly generated bytes.

2. The data storage device of claim 1 , wherein the memory access operation is a read operation.

3. The data storage device of claim 1 , wherein the memory access operation is a write operation.

4. The data storage device of claim 3 , wherein the data verification circuit is further configured to:
issue a commit operation command to write the transferred bytes to an array within one or more of the memory dies,
determine whether the transfer status fail bit is set,
generate an indication of a failure in the write operation based on determining that the transfer status fail bit is set; and
prevent a commit operation in response to determining that the transfer status fail bit is set.

5. The data storage device of claim 4 , wherein the memory block is further configured to transmit the failure indication to the controller.

6. The data storage device of claim 1 , wherein the predetermined number of bytes is based on a data size associated with the memory access command.

7. The data storage device of claim 1 , wherein the data verification circuit is part of the memory block.

8. A method performed by a data storage device having a controller coupled to a non-volatile memory device, the method comprising:
receiving a memory access command from an external device;
performing a memory access operation based on the memory access command;
determining a number of bytes that is transferred to the memory device during the memory access operation;
determining whether the number of transferred bytes is equal to a predetermined number of bytes;
in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes, appending a number of additional bytes to the transferred bytes, wherein the number of additional bytes is equal to a difference between the predetermined number of bytes and the number of transferred bytes; and
in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes, setting a transfer status fail bit indicating that the number of transferred bytes is not equal to the predetermined number of bytes,
wherein the number of additional bytes are one of randomly generated bytes, logic high bytes, and logic low bytes.

9. The method of claim 8 , wherein the memory access operation is read operation.

10. The method of claim 8 , wherein the memory access operation is a write operation.

11. The method of claim 10 , further comprising:
issue a commit operation command to write the bytes to an array within one or more memory dies;
determine whether the transfer status fail bit is set;
generate an indication of a failure in the write operation based on determining that the transfer status fail bit is set; and
prevent a commit operation associated with the commit operation command in response to determining that the transfer status fail bit is set.

12. The method of claim 11 , further comprising storing the indication in a memory of the controller.

13. The method of claim 12 , wherein the predetermined number of bytes is based on a data size associated with the memory access command.

14. An apparatus, comprising:
means for receiving a memory access command from a controller;
means for performing a memory access operation based on the memory access command;
means for determining a number of bytes that is transferred during the memory access operation;
means for determining whether the number of transferred bytes is equal to a predetermined number of bytes;
means for appending a second number of additional bytes to transferred bytes in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes, wherein the second number of additional bytes is equal to a difference between the predetermined number of bytes and the number of transferred bytes; and
means for setting a transfer status fail bit indicating that the number of transferred bytes is not equal to the predetermined number of bytes in response to determining that the number of transferred bytes is not equal to the predetermined number of bytes,
wherein the second number of additional bytes are randomly generated bytes.

15. The apparatus of claim 14 , wherein the memory access operation is a read operation.

16. The apparatus of claim 14 , wherein the memory access operation is a write operation, the apparatus further comprising:
means for issuing a commit operation command to write the transferred bytes to an array within one or more memory dies;
means for determining whether the transfer status fail bit is set;
means for generating an indication of a failure in the write operation based on determining that the transfer status fail bit is set; and
means for preventing a commit operation associated with the commit operation command in response to determining that the transfer bit is set.

17. The apparatus of claim 16 , wherein the predetermined number of bytes is based on a data size associated with the memory access command.

Assignees

• Western Digital Tech Inc

Inventors

• Linnen Daniel
• Sangoi Aashish
• Periyannan Kirubakaran
• Hahn Judah Gamliel

Classifications

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title