Storage device and method for processing power disable signal

Patent metadata

Field	Value
Publication number	US-9684359-B2
Application number	US-201514817359-A
Country	US
Kind code	B2
Filing date	Aug 4, 2015
Priority date	Oct 31, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A storage device for connection with a host device via an interface bus, includes a storage unit and a storage controller configured to control access to the storage unit and receive a power disable signal from the host device. The storage controller includes a plurality of processing units, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal.

First claim

What is claimed is:

1. A storage device for connection with a host device, comprising:
a storage device;
a volatile memory; and
a storage controller configured to control access to the storage device and connected to a bus through which a power disable signal is received from the host device, wherein
the storage controller includes a plurality of processors, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal, and
one of the processors initiates the power disable processing after reception of the interrupt signal, the power disable processing including backup of data stored in the storage controller into the volatile memory.

2. The storage device according to claim 1 , wherein
the storage controller further includes a register,
one or more of the processors access the register, in response to reception of the interrupt signal, and
one of the processors that accesses the register first while a predetermined flag is set in the register initiates the power disable processing.

3. The storage device according to claim 1 , further comprising:
a plurality of interrupt controllers, each configured to output the interrupt signal to one of the processors corresponding thereto, in response to the assertion of the power disable signal.

4. The storage device according to claim 1 , further comprising:
a power supply controller configured to supply power to the volatile memory while the power disable signal is asserted.

5. The storage device according to claim 4 , wherein
the power supply controller is further configured to supply power to the storage controller,
the one of the processors outputs a signal requesting the power supply controller to stop power supply to the storage controller after the backup of the data is completed, and
the power supply controller stops the power supply to the storage controller in response to receiving the signal.

6. The storage device according to claim 5 , wherein
the power supply controller is further configured to resume power supply to the storage controller after the power disable signal is deasserted, and
the storage controller causes the storage device to be initialized after the power supply to the storage controller is resumed.

7. The storage device according to claim 6 , wherein
the power supply controller is further configured to transmit a valid state signal to the storage controller after the power supply to the storage controller is resumed, and
the storage controller does not cause the volatile memory to be initialized when the valid state signal is received.

8. The storage device according to claim 1 , wherein the volatile memory includes a buffer area for temporarily storing data to be written to the storage device and data read from the storage device.

9. The storage device according to claim 1 , wherein the data stored in the storage controller includes status information indicating a status of the storage controller and log information indicating an operation history of the storage controller.

10. The storage device according to claim 1 , wherein
the storage device is a magnetic disk.

11. The storage device according to claim 1 , wherein
the storage device is a nonvolatile semiconductor memory.

12. A storage device for connection with a host device, comprising:
a first storage;
a second storage that is volatile; and
a storage controller configured to control access to the first storage and connected to a bus through which a power disable signal is received from the host device, wherein
the storage controller includes a plurality of processors, each of which receives an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal, and
one of the processors initiates the power disable processing after reception of the interrupt signal, the power disable processing including backup of data stored in the storage controller into the second storage.

13. An operating method of a storage device having a storage device, a volatile memory, and a storage controller including a plurality of processors, the method comprising:
receiving, at the storage controller, a power disable signal from a host device;
receiving, at each of the processors, an interrupt signal to initiate power disable processing, in response to assertion of the power disable signal; and
initiating, at one of the processors, the power disable processing, after the assertion of the power disable signal, the power disable processing including backup of data stored in the storage controller into the volatile memory.

14. The method according to claim 13 , wherein the storage controller further includes a register, the method further comprising:
accessing the register from one or more of the processors, in response to reception of the interrupt signal, wherein
the power disable processing is initiated by one of the processors that accesses the register first while a predetermined flag is set in the register.

15. The method according to claim 13 , further comprising:
supplying power to the volatile memory while the power disable signal is asserted.

16. The method according to claim 15 , further comprising:
outputting, from the one of the processors, a signal requesting a power supply controller to stop power supply to the storage controller after the backup of the data is completed; and
stopping power supply to the storage controller in response to receiving the signal.

17. The method according to claim 16 , further comprising:
resuming power supply to the storage controller after the power disable signal is deasserted; and
initializing the storage device after the power supply to the storage controller is resumed.

18. The method according to claim 17 , further comprising:
transmitting a valid state signal to the storage controller after the power supply to the storage controller is resumed,
wherein the volatile memory is not initialized when the valid state signal is received.

19. The method according to claim 13 , further comprising:
temporarily storing data to be written to the storage device and data read from the storage device in a buffer area of the volatile memory.

20. The method according to claim 13 , wherein the data stored in the storage controller includes status information indicating a status of the storage controller and log information indicating an operation history of the storage controller.

Assignees

• Toshiba Kk

Inventors

• Kunishige Shinji

Classifications

• G06F1/3246

  by software initiated power-off · CPC title

• G06F1/3268 Primary

  Power saving in hard disk drive · CPC title

• G06F1/3221

  of disk drive devices · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title