Semiconductor device package, antenna device, and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11830799-B2
Application number	US-202117223932-A
Country	US
Kind code	B2
Filing date	Apr 6, 2021
Priority date	Apr 6, 2021
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a dielectric layer, an electronic component, a first conductive layer, and a conductive element. The dielectric layer has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the dielectric layer. The first conductive layer is embedded in the dielectric layer and adjacent to the first surface of the dielectric layer. The conductive element is disposed on the first surface of the dielectric layer and in contact with the first conductive layer.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a first dielectric layer having a first surface and a second surface opposite to the first surface,
an electronic component embedded in the first dielectric layer and having a first lateral surface and a second lateral surface adjacent to the first lateral surface;
a plurality of first conductive layers embedded in the first dielectric layer and adjacent to the first surface of the first dielectric layer;
a plurality of conductive elements disposed on the first surface of the first dielectric layer and in contact with the first conductive layers,
wherein from a bottom view, a number of the conductive elements projected on the first lateral surface is less than a number of the conductive elements projected on the second lateral surface.

2. An antenna device, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface,
an antenna disposed on the second surface of the dielectric layer;
a first conductive layer disposed in the dielectric layer;
a conductive element disposed on the first surface of the dielectric layer and electrically connected to the antenna through the first conductive layer,
wherein the first conductive layer has a first portion exposed from the conductive element and a second portion in contact with the conductive element, and
wherein the first conductive layer traverses in the dielectric layer in a direction parallel to the first surface of the dielectric layer; and
a solder ball, wherein a projecting area of the solder ball on the first surface of the dielectric layer is non-overlapping with a projecting area of the conductive element on the first surface of the dielectric layer, and wherein the solder ball is electrically connected to the conductive element through the first conductive layer.

3. The semiconductor device package of claim 1 , wherein a width of the conductive elements is smaller than a width of the first conductive layers from the bottom view.

4. The semiconductor device package of claim 3 , wherein the first conductive layers have a lower surface partially exposed by the conductive elements.

5. The semiconductor device package of claim 4 , wherein the first conductive layers have a first portion overlapping the conductive elements in a direction perpendicular to the first surface of the first dielectric layer and a second portion exposed by the conductive elements, and wherein an area of the first portion is smaller than that of the second portion.

6. The semiconductor device package of claim 1 , wherein the first dielectric layer has a first portion embedding the first conductive layers and the electronic component includes a second dielectric layer disposed over an active surface of the electronic component and connected to the first portion of the first dielectric layer, and wherein the conductive elements has a plurality of conductive vias tapering toward the electronic component and extending through the first portion of the first dielectric layer, and the plurality of conductive vias are partially disposed in the second dielectric layer.

7. The semiconductor device package of claim 6 , wherein the conductive elements have a first seed layer disposed over a surface of the plurality of conductive vias and connecting a plurality of conductive pads of the electronic component with the plurality of conductive vias, and wherein a portion of the first seed layer is disposed under the first portion of the first dielectric layer.

8. The semiconductor device package of claim 7 , wherein the conductive elements have a second seed layer disposed between the first portion of the first dielectric layer and the first seed layer, and wherein the second seed layer is in contact with a lower surface of the first portion of the first dielectric layer and a lower surface of each of the first conductive layers.

9. The semiconductor device package of claim 1 , further comprising a shielding layer covering the electronic component and having a discontinuous pattern with at least three gaps, wherein two of the at least three gaps overlap the electronic component in a cross-sectional view.

10. The semiconductor device package of claim 9 , further comprising a first conductive via connecting the shielding layer and having a shape tapering toward the first conductive layers, wherein each of the conductive elements has a second conductive via having a shape tapering in an opposite direction of the shape of the first conductive via.

11. The semiconductor device package of claim 9 , further comprising a plurality of antenna units disposed over the shielding layer and electrically connected to the conductive elements through the first conductive layers, wherein a portion of the antenna units overlaps the at least three gaps in the cross-sectional view.

12. The semiconductor device package of claim 1 , further comprising a plurality of connection elements connected to the first conductive layers, wherein the conductive elements includes at least four conductive elements disposed directly below the electronic component and spaced apart from each other, wherein the at least four conductive elements do not extend over a lateral surface of the electronic component in a cross-sectional view, and wherein the connection elements surrounds the at least four conductive elements.

13. The semiconductor device package of claim 12 , wherein the at least four conductive elements are non-overlapping with the first conductive layers in the cross-sectional view.

14. The antenna device of claim 2 , wherein the first conductive layer has a long side extending parallel to the first surface of the dielectric layer.

15. The antenna device of claim 14 , wherein the first conductive layer has a short side connected to the long side and extending perpendicular to the first surface of the dielectric layer, wherein the short side is shorter than the long side.

16. An antenna device, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface,
an antenna disposed on the second surface of the dielectric layer;
a first conductive layer disposed in the dielectric layer;
a conductive element disposed on the first surface of the dielectric layer and electrically connected to the antenna through the first conductive layer,
wherein the first conductive layer has a first portion exposed from the conductive element and a second portion in contact with the conductive element, and
wherein the first conductive layer traverses in the dielectric layer in a direction parallel to the first surface of the dielectric layer; and
an electronic component embedded in the dielectric layer, wherein an upper surface and a lower surface of the first conductive layer are at elevations higher than the conductive element and lower than the electronic component from a cross-sectional view.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title