Selective capping processes and structures formed thereby

Patent metadata

Field	Value
Publication number	US-11830742-B2
Application number	US-202217853600-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Nov 28, 2017
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure in a dielectric layer, wherein the gate structure comprises a metal gate electrode embedded within a gate dielectric layer;
recessing the metal gate electrode to expose a sidewall of the gate dielectric layer;
selectively reacting a reactant with a top surface and the sidewall of the gate dielectric layer to form a monolayer of a hydrophobic material; and
after forming the monolayer, depositing a capping layer onto the metal gate electrode.

2. The method of claim 1 , wherein the reactant comprises tetramethylsilane (Si(CH 3 ) 4 ).

3. The method of claim 1 , wherein the reactant comprises N,N-dimethyltrimethylsilylamine ((CH 3 ) 2 —N—Si—(CH 3 ) 3 ).

4. The method of claim 1 , wherein the reactant comprises a silane derivative.

5. The method of claim 1 , wherein the capping layer is a tungsten layer having a chlorine concentration of less than about 1%.

6. The method of claim 1 , wherein the monolayer comprises a bottom surface in physical contact with the metal gate electrode.

7. The method of claim 1 , wherein the capping layer comprises a sidewall in physical contact with a sidewall of the monolayer.

8. A method of manufacturing a semiconductor device, the method comprising:
depositing a dielectric layer over a source/drain region;
forming a gate structure planar with the dielectric layer, wherein the gate structure comprises a metal gate electrode and a gate dielectric layer, the metal gate electrode being wrapped by the gate dielectric layer;
recessing the metal gate electrode to form a recessed metal gate electrode and expose a sidewall of the gate dielectric layer;
exposing a top surface and the sidewall of the gate dielectric layer to a silane derivative with one or more hydrophobic functional groups; and
exposing the recessed metal gate electrode to a tungsten precursor.

9. The method of claim 8 , wherein the exposing the recessed metal gate electrode to the tungsten precursor forms a capping layer over the metal gate electrode, wherein a width of the capping layer is smaller than a width of the recessed metal gate electrode.

10. The method of claim 9 , wherein the capping layer has a chlorine concentration of less than about 1%.

11. The method of claim 9 , wherein the exposing the top surface and the sidewall of the gate dielectric layer to the silane derivative with one or more hydrophobic functional groups forms a layer of a hydrophobic material over the top surface and the sidewall of the gate dielectric layer, and the capping layer has a sidewall in physical contact with a sidewall of the layer of the hydrophobic material.

12. The method of claim 8 , further comprising exposing a top surface of the dielectric layer with the silane derivative with one or more hydrophobic functional groups.

13. The method of claim 8 , the recessing the metal gate electrode creates a recess that has a depth in a range from 30 Å to 50 Å.

14. The method of claim 13 , wherein the exposing the recessed metal gate electrode to the tungsten precursor forms a capping layer over the metal gate electrode, wherein the capping layer has a thickness in a range from 30 Å to 50 Å.

15. A method of manufacturing a semiconductor device, the method comprising:
forming a metal gate structure within a dielectric layer, wherein the metal gate structure comprises a metal gate electrode and a gate dielectric layer, wherein the metal gate electrode has a top surface lower than a top surface of the gate dielectric layer such that a cavity is formed in the gate dielectric layer and over the metal gate electrode, the cavity exposing a sidewall of the gate dielectric layer;
forming a monolayer of a hydrophobic material over a top surface and the sidewall of the gate dielectric layer; and
forming a capping layer over the metal gate electrode.

16. The method of claim 15 , wherein the monolayer extends over a top surface of the dielectric layer.

17. The method of claim 15 , wherein the metal gate electrode comprises an electrode layer and a metal layer, wherein the metal layer is disposed between the electrode layer and the gate dielectric layer and surrounds sidewalls of the electrode layer, wherein an end of the monolayer is in physical contact with the metal layer.

18. The method of claim 17 , wherein a top surface of the metal layer is partially covered by the capping layer.

19. The method of claim 17 , wherein the sidewall of the gate dielectric layer comprises an upper portion and a bottom portion, wherein the upper portion of the sidewall of the gate dielectric layer is covered by the monolayer, and the bottom portion of the sidewall of the gate dielectric layer is covered by the metal layer.

20. The method of claim 15 , wherein the capping layer has a concentration of chlorine that is less than 1%.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chi Chih-Chien
• Lee Pei-Hsuan
• Su Hung-Wen
• Wei Hsiao-Kuan
• CHIEN Jui-Fen
• Hsu Hsin-Yun

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P90/1912

  using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon · CPC title

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title