Memory device

Patent metadata

Field	Value
Publication number	US-11830558-B2
Application number	US-202217742142-A
Country	US
Kind code	B2
Filing date	May 11, 2022
Priority date	Aug 27, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell area in which a first MAT (Memory Array Tile) and a second MAT are disposed, each of the first MAT and the second MAT including a plurality of wordlines stacked on a first substrate in a vertical direction perpendicular to an upper surface of the first substrate and a plurality of channel structures penetrating the plurality of wordlines by extending in the vertical direction and connected to the first substrate;
a peripheral circuit area stacked with the memory cell area in the vertical direction, and including a second substrate and a plurality of semiconductor elements disposed on the second substrate;
a first local lockout circuit configured to determine whether to lock out the first MAT during an operation of the first MAT; and
a second local lockout circuit configured to determine whether to lock out the second MAT, separately from the first MAT, during an operation of the second MAT.

2. The memory device of claim 1 , wherein the first local lockout circuit and the second local lockout circuit are disposed on the upper surface of the first substrate.

3. The memory device of claim 1 , wherein the first local lockout circuit is disposed in a region of the peripheral circuit area, stacked with first MAT, and
the second local lockout circuit is disposed in a region of the peripheral circuit area, stacked with second MAT.

4. The memory device of claim 1 , further comprising:
a pad area disposed on one side of the memory cell area and including at least one power pad receiving an external power voltage,
wherein the first MAT is connected to the power pad by a first power wiring and the second MAT is connected to the power pad by a second power wiring.

5. The memory device of claim 4 , wherein the first local lockout circuit compares a first operating voltage supplied to the first MAT by the first power wiring with a first lockout voltage, and
the second local lockout circuit compares a second operating voltage supplied to the second MAT by the second power wiring with a second lockout voltage.

6. The memory device of claim 5 , wherein a length of the first power wiring is different from a length of the second power wiring, and
a level of the first lockout voltage is different form a level of the second lockout voltage.

7. A memory device, comprising:
a memory cell area in which a first MAT (Memory Array Tile) and a second MAT are disposed, each of the first MAT and the second MAT including a plurality of wordlines stacked on a first substrate in a vertical direction perpendicular to an upper surface of the first substrate and a plurality of channel structures penetrating the plurality of wordlines by extending in the vertical direction and connected to the first substrate;
a peripheral circuit area including a second substrate and a plurality of circuit elements disposed on the second substrate, and being in contact with a lower surface of the first substrate in the vertical direction;
a first local lockout circuit configured to determine whether to lock out the first MAT during an operation of the first MAT; and
a second local lockout circuit configured to determine whether to lock out the second MAT, separately from the first MAT, during an operation of the second MAT,
wherein the plurality of circuit elements are disposed between the first substrate and the second substrate.

8. An operating method of a memory device including a memory cell area in which a first MAT (Memory Array Tile) and a second MAT are disposed on a first substrate, a peripheral circuit area including peripheral circuits controlling the first MAT and the second MAT and stacked with the memory cell area in a vertical direction perpendicular to an upper surface of the first substrate, and a pad area receiving an external power voltage, comprising:
activating a second local lockout control signal, by a second local lockout circuit corresponding to the second MAT and maintaining a first local lockout control signal as a deactivated state, by a first local lockout circuit corresponding to the first MAT, when a second operating voltage is decreased based a decrease of the external power voltage;
stopping an operation of the second MAT, by the peripheral circuits of the peripheral circuit area, in response to the activation of the second local lockout control signal; and
performing recovery for the second MAT, by the peripheral circuits of the peripheral circuit area.

9. The operating method of claim 8 , wherein the second local lockout circuit compares the second operating voltage with a second local lockout voltage, and activates the second local lockout control signal when a level of the second operating voltage is smaller than a level of the second local lockout voltage.

10. The operating method of claim 8 , wherein the peripheral circuits of the peripheral circuit area perform recovery for the second MAT, when a recovery signal for the second MAT is activated after the second local lockout control signal is activated and a predetermined time is elapsed.

11. The operating method of claim 8 , wherein the peripheral circuits of the peripheral circuit area stop operations of the first MAT and the second MAT, when a global lockout control signal is activated by a global lockout circuit different from a first local lockout circuit corresponding to the first MAT and a second local lockout circuit, after the second local lockout control signal is activated.

12. The operating method of claim 11 , wherein the peripheral circuits of the peripheral circuit area perform recovery for the first MAT and the second MAT, when recovery signals for the first MAT and the second MAT are activated after the global lockout control signal is activated and a predetermined time is elapsed.

13. The operating method of claim 11 , wherein a recovery signal for the second MAT is activated longer than a recovery signal for the first MAT.

14. The operating method of claim 13 , wherein the recovery signal for the second MAT is deactivated at the same time as the recovery signal for the first MAT.

15. The operating method of claim 11 , wherein the global lockout circuit activates the global lockout control signal when a global lockout voltage generated by the external power voltage is smaller than a global lockout voltage, and
a level of the global lockout voltage is smaller than a level of the second local lockout voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shim Sangwon
• Park Sangwon
• Lim Bongsoon
• Choi Yoonhee

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title