Adjustable voltage drop detection threshold in a memory device

Patent metadata

Field	Value
Publication number	US-10629288-B2
Application number	US-201816017315-A
Country	US
Kind code	B2
Filing date	Jun 25, 2018
Priority date	Jun 25, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.

First claim

The invention claimed is:

1. A method comprising:
dynamically establishing a voltage drop detection threshold of a memory device, wherein a power loss event is triggered when a supply voltage falls below the voltage drop detection threshold, wherein the establishing comprises:
collecting an error parameter associated with performing multiple memory operations on the memory device, wherein the multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device;
determining whether the error parameter is below an allowable error threshold; and
in response to determining that the error parameter is below the allowable error threshold, establishing the voltage drop detection threshold at a voltage level less than the first supply voltage level.

2. The method of claim 1 , wherein the voltage drop detection threshold is established at the second supply voltage level.

3. The method of claim 1 , wherein the voltage drop detection threshold is established at a voltage level between the first supply voltage level and the second supply voltage level, wherein the voltage level is one or two digital-to-analog converter steps lower than the first supply voltage level.

4. The method of claim 1 further comprising establishing an initial voltage drop detection threshold of the memory device in reference to the first supply voltage level established as the first operating voltage for the memory device, wherein the establishing of the voltage drop detection threshold at the voltage level less than the first supply voltage level comprises changing the initial voltage drop detection threshold.

5. The method of claim 1 further comprising performing multiple initial memory operations on the memory device while applying the first operating voltage at the first supply voltage level before the collecting of the error parameter in response to memory operations performed while applying the supply voltage at the second supply voltage level.

6. The method of claim 1 , wherein the memory device comprises a NAND storage device, wherein the error parameter represents data bus errors of the memory device, and wherein collecting the error parameter comprises assessing a bit-error-rate associated with reading back data from NAND latches of the NAND storage device.

7. The method of claim 1 further comprising:
detecting a power loss event that occurs when a given memory operation is being performed;
determining a given error parameter associated with performing the given memory operation again after the power loss event;
in response to determining that the given error parameter is below the allowable error threshold, updating a false positive trigger statistic; and
in response to determining that the given error parameter exceeds the allowable error threshold, maintaining the established voltage drop detection threshold at the voltage level.

8. The method of claim 7 further comprising in response to determining the false positive trigger statistic exceeds a false positive trigger threshold, changing the established voltage drop detection threshold.

9. The method of claim 1 further comprising in response to determining that the error parameter exceeds the allowable error threshold:
collecting a second error parameter associated with performing of the multiple memory operations while applying the supply voltage at the second supply voltage level;
determining whether the second error parameter exceeds the allowable error threshold;
in response to determining the second error parameter exceeds the allowable error threshold, establishing the voltage drop detection threshold at a voltage level greater than the second supply voltage level by a first amount; and
in response to determining the second error parameter is below the allowable error threshold, establishing the voltage drop detection threshold at a voltage level greater than the second supply voltage level by a second amount, the second amount being greater than the first amount.

10. The method of claim 1 , wherein the memory device is configured to operate in a multiple of modes, wherein the voltage drop detection threshold is a first voltage drop detection threshold, further comprising associating the first voltage drop detection threshold with a first of the multiple modes and establishing a second voltage drop detection threshold for a second of the multiple modes.

11. A system comprising:
control circuitry for:
dynamically establishing a voltage drop detection threshold of a memory device, wherein a power loss event is triggered when a supply voltage falls below the voltage drop detection threshold, wherein the establishing comprises:
collecting an error parameter associated with performing multiple memory operations on the memory device, wherein the multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device;
determining whether the error parameter is below an allowable error threshold; and
in response to determining that the error parameter is below the allowable error threshold, establishing the voltage drop detection threshold at a voltage level less than the first supply voltage level.

12. The system of claim 11 , wherein the voltage drop detection threshold is established at the second supply voltage level.

13. The system of claim 11 , wherein the voltage drop detection threshold is established at a voltage level between the first supply voltage level and the second supply voltage level, wherein the voltage level is one or two digital-to-analog converter steps lower than the first supply voltage level.

14. The system of claim 11 , wherein the control circuitry is further for establishing an initial voltage drop detection threshold of the memory device in reference to the first supply voltage level established as the first operating voltage for the memory device, wherein the establishing of the voltage drop detection threshold at the voltage level less than the first supply voltage level comprises changing the initial voltage drop detection threshold.

15. The system of claim 11 , wherein the control circuitry is further for performing multiple initial memory operations on the memory device while applying the first operating voltage at the first supply voltage level before the collecting of the error parameter in response to memory operations performed while applying the supply voltage at the second supply voltage level.

16. The system of claim 11 , wherein the memory device comprises a NAND storage device, wherein the error parameter represents data bus errors of the memory device, and wherein collecting the error parameter comprises assessing a bit-error-rate associated with reading back data from NAND latches of the NAND storage device.

17. The system of claim 11 , wherein the control circuitry is further for:
detecting a power loss event that occurs when a given memory operation is being performed;
determining a given error parameter associated with performing the given memory operation again after the power loss event;
in response to determining that the given error parameter is below the allowable error threshold, updating a false positive trigger statistic; and
in response to determining that the given error parameter exceeds the allowable error threshold, maintaining the establishe

Assignees

• Micron Technology Inc

Inventors

• Cariello Giuseppe

Classifications

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G11C5/143 Primary

  Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence) · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title