Memory device

Patent metadata

Field	Value
Publication number	US-11355205-B2
Application number	US-202117172288-A
Country	US
Kind code	B2
Filing date	Feb 10, 2021
Priority date	Aug 27, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

First claim

What is claimed is:

1. A memory device comprising:
a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit controlling the first memory cells and disposed below the first memory cell array;
a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit controlling the second memory cells and disposed below the second memory cell array; and
a pad area including a power wiring, wherein:
the first memory area includes a first local lockout circuit determining whether to lock out during an operation of the first memory area,
the second memory area includes a second local lockout circuit determining whether to lock out separately from the first memory area during an operation of the second memory area,
the first memory area and the second memory area are included in a single semiconductor chip to share the pad area, and
while the first memory area performs a first operation, the second memory area performs a second operation, and each of the first operation and the second operation is a program operation, a read operation, or an erase operation.

2. The memory device of claim 1 , wherein:
the first local lockout circuit generates a first lockout control signal,
the first peripheral circuit stops the first operation of the first memory area and performs recovery of the first memory area, when the first lockout control signal is activated,
the second local lockout circuit individually generates a second lockout control signal, and
the second peripheral circuit stops the second operation of the second memory area and performs recovery of the second memory area, when the second lockout control signal is activated.

3. The memory device of claim 2 , wherein:
the first local lockout circuit activates the first lockout control signal when a first operating voltage of the first memory area is lower than a lockout voltage during the first operation of the first memory area, and
the second local lockout circuit activates the second lockout control signal when a second operating voltage of the second memory area is lower than a lockout voltage during the second operation of the second memory area.

4. The memory device of claim 3 , wherein the lockout voltage during the first operation of the first memory area and the lockout voltage during the second operation of the second memory area are respectively determined according to an operation performed in the first memory area and the second memory area.

5. The memory device of claim 1 , wherein the first memory area operates at a first operating voltage and the second memory area operates at a second operating voltage different from the first operating voltage.

6. The memory device of claim 5 , wherein:
the first operating voltage is determined depending on a length of a first power wiring connecting a power pad receiving external power and the first memory area,
the second operating voltage is determined depending on a length of a second power wiring connecting the power pad and the second memory area, and
the length of the first power wiring is shorter than the length of the second power wiring.

7. The memory device of claim 1 , wherein a magnitude of a voltage drop occurring in the first memory area performing the first operation is different from a magnitude of a voltage drop occurring in the second memory area performing the second operation.

8. The memory device of claim 7 , wherein each of the first local lockout circuit and the second local lockout circuit includes a variable resistor configured to adjust an operating voltage depending on operations of the first memory area and the second memory area.

9. The memory device of claim 1 , wherein the first local lockout circuit and the second local lockout circuit are disposed in positions in which a length of each of wirings extending from a power pad to the first local lockout circuit and the second local lockout circuit is relatively shortest.

10. The memory device of claim 1 , further comprising:
a global lockout circuit disposed in the pad area, wherein
the global lockout circuit determines whether to lock out both the first memory area and the second memory area.

11. The memory device of claim 10 , wherein the global lockout circuit generates a global lockout control signal according to a level of a global operating voltage.

12. The memory device of claim 11 , wherein the global operating voltage is different from an operating voltage of the first memory area and an operating voltage of the second memory area.

13. The memory device of claim 11 , wherein the global lockout circuit activates the global lockout control signal when the global operating voltage is lower than a global lockout voltage.

14. The memory device of claim 13 , wherein when the global lockout control signal is not activated and a lockout control signal corresponding to the first memory area or the second memory area is activated, each of the first peripheral circuit and the second peripheral circuit stops an operation of a memory area corresponding to the lockout control signal that is activated and performs recovery of the memory area.

15. The memory device of claim 13 , wherein when the global lockout control signal is activated, the first peripheral circuit and the second peripheral circuit stop operations of the first memory area and the second memory area and perform recovery of each of the first memory area and the second memory area.

16. A memory device comprising:
a memory cell area including a plurality of Memory Array Tiles (MATs) each including a plurality of memory cells;
a peripheral circuit area disposed below the memory cell area; and
a pad area disposed on a side surface of the memory cell area and including a power wiring, wherein:
the plurality of MATs perform an operation individually by an operating voltage applied based on external power,
the peripheral circuit area individually stops the operation and performs recovery, when the operating voltage is lower than a lockout voltage during the operation of the plurality of MATs, and
the memory cell area includes at least two MATs having the operating voltage and the lockout voltage different from each other.

17. A memory device comprising:
a memory cell area including a first metal pad;
a peripheral circuit area including a second metal pad;
a pad area disposed on a side surface of the memory cell area and including a wiring applying external power to the peripheral circuit area;
a plurality of Memory Array Tiles (MATs) included in the memory cell area and each including a plurality of memory cells; and
a lockout circuit respectively disposed in the plurality of MATs or in the peripheral circuit area below the plurality of MATs, wherein:
the peripheral circuit area is vertically connected to the memory cell area by the first metal pad and the second metal pad and applies an operating voltage to the plurality of MATs, based on the external power applied from the pad area,
the plurality of MATs operate individually by the operating voltage, and
the lockout circuit individually determines whether to lock out the plurality of MATs.

18. The memory device of claim 17 , wherein the first metal pad and the second metal pad are formed of copper.

19. The memory device of claim 17 , wherein the first metal pad and the second metal pad are connected in a bonding manner.

20. The memory device of claim 17 , wherein the memory

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shim Sangwon
• Park Sangwon
• Lim Bongsoon
• Choi Yoonhee

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title