Shift register unit, shift register, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-2017193938-A1
Application number	US-201615251199-A
Country	US
Kind code	A1
Filing date	Aug 30, 2016
Priority date	Jan 5, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The present disclosure provides a shift register unit, a shift register, a gate driving circuit and a display apparatus. The shift register unit comprises an input module, a pull-up module, a pull-down module, a pull-down control module and a storage module. With the above shift register unit according to the present disclosure, it is possible to reduce noise in an output signal, so as to improve the accuracy of the output signal. On the other hand, it is possible to provide a reduced number of TFTs, a simplified circuit structure, a decreased area to be occupied, and thus a narrowed width of a rim of a display apparatus.

First claim

What is claimed is:

1 . A shift register unit, comprising:
an input module having a control terminal connected to a signal input terminal, an input terminal connected to a first voltage input terminal, and an output terminal connected to a pull-up node, the input module being configured to provide a signal at the first voltage input terminal to the pull-up node under control of the signal input terminal; a pull-up module having a control terminal connected to the pull-up node, an input terminal connected to a clock signal input terminal, and an output terminal connected to a signal output terminal of the shift register unit, the pull-up module being configured to pull up an output signal at the signal output terminal under control of the pull-up node; a pull-down control module having a first control terminal and a first input terminal connected to the clock signal input terminal, a first output terminal and a second input terminal connected to a pull-down node, a second control terminal connected to the signal output terminal, and a second output terminal connected to a low level input terminal, the pull-down control module being configured to maintain the pull-down node at a low level under joint control of the clock signal input terminal and the signal output terminal; a pull-down module having a first control terminal and a second control terminal connected to the pull-down node, a first input terminal connected to the signal output terminal, a second input terminal connected to the pull-up node, a first output terminal and a second output terminal connected to the low level input terminal, the pull-down module being configured to pull down the output signal at the signal output terminal under control of the pull-down node; and a storage module having a terminal connected to the pull-up node and another terminal connected to the low level input terminal, the storage module being configured to stabilize a potential at the pull-up node.

2 . The shift register unit of claim 1 , wherein the input module comprises a first transistor having its gate serving as the control terminal of the input module, its source serving as the input terminal of the input module, and its drain serving as the output terminal of the input module.

3 . The shift register unit of claim 1 , further comprising:
a reset module having a control terminal connected to a reset signal input terminal, an input terminal connected to the pull-up node, and an output terminal connected to a second voltage input terminal, the reset module being configured to reset the control terminal of the pull-up module.

4 . The shift register unit of claim 3 , wherein the reset module comprises a second transistor having its gate serving as the control terminal of the reset module, its source serving as the input terminal of the reset module, and its drain serving as the output terminal of the reset module, and
wherein a low level signal can be inputted at the second voltage input terminal.

5 . The shift register unit of claim 1 , wherein the pull-up module comprises a third transistor having its gate serving as the control terminal of the pull-up module, its source serving as the input terminal of the pull-up module, and its drain serving as the output terminal of the pull-up module.

6 . The shift register unit of claim 1 , wherein the pull-down module comprises a fourth transistor having its gate serving as the first control terminal of the pull-down module, its source serving as the first input terminal of the pull-down module, and its drain serving as the first output terminal of the pull-down module.

7 . The shift register unit of claim 6 , wherein the pull-down module further comprises a seventh transistor having its gate serving as the second control terminal of the pull-down module, its source serving as the second input terminal of the pull-down module, and its drain serving as the second output terminal of the pull-down module.

8 . The shift register unit of claim 1 , wherein the pull-down control module comprises:
a fifth transistor having its gate and source serving as the first control terminal and the first input terminal of the pull-down control module, respectively, and its drain serving as the output terminal of the pull-down control module; and a sixth transistor having its gate serving as the second control terminal of the pull-down control module, its source serving as the second input terminal of the pull-down control module, and its drain serving as the second input terminal of the pull-down control module, and wherein the fifth transistor has a smaller width-to-length ratio than the sixth transistor.

9 . The shift register unit of claim 8 , wherein a ratio of the width-to-length ratio of the fifth transistor to that of the sixth transistor ranges from 1:3 to 1:5.

10 . The shift register unit of claim 3 , wherein, when a high level voltage is inputted at the first voltage input terminal, a low level voltage is inputted at the second voltage input terminal; or when a low level voltage is inputted at the first voltage input terminal, a high level voltage is inputted at the second voltage input terminal.

11 . The shift register unit of claim 1 , wherein the storage module comprises a capacitor having a terminal connected to the pull-up node and another terminal connected to the low level input terminal.

12 . A shift register, comprising a plurality of stages of cascaded shift register units each according to claim 1 .

13 . A gate driving circuit, comprising the shift register according to claim 12 .

14 . A display apparatus, comprising the gate driving circuit according to claim 13 .

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Feng Silin
• Li Hongmin

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G2300/0465

  Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/36

  using liquid crystals · CPC title