Shift register circuit, gate driving circuit and method for driving the same, and display apparatus

Patent metadata

Field	Value
Publication number	US-2020184872-A1
Application number	US-201916523215-A
Country	US
Kind code	A1
Filing date	Jul 26, 2019
Priority date	Dec 7, 2018
Publication date	Jun 11, 2020
Grant date	—

Abstract

A shift register circuit, a gate driving circuit and a method for driving the same, and a display apparatus are disclosed. The shift register circuit includes: an input circuit configured to receive an input signal and output the input signal to a pull-up node; an output circuit configured to receive a clock signal and provide an output signal at a signal output terminal based on the clock signal under control of a level at the pull-up node; a pull-down circuit configured to pull down a level at the signal output terminal under control of a level at a pull-down node; and at least one of a feedback circuit or a pull-down control circuit, wherein the feedback circuit is electrically coupled to the pull-up node, and is configured to output a first feedback signal based on the level at the pull-up node; and the pull-down control circuit is electrically coupled to the pull-up node and the pull-down node, and is configured to receive a second feedback signal and control the level at the pull-down node under control of the level at the pull-up node and the second feedback signal.

First claim

I/We claim:

1 . A shift register circuit, comprising:
an input circuit electrically coupled to a pull-up node of the shift register circuit, and configured to receive an input signal and output the input signal to the pull-up node; an output circuit electrically coupled to a signal output terminal and the pull-up node of the shift register circuit, and configured to receive a clock signal and provide an output signal at the signal output terminal based on the clock signal under control of a level at the pull-up node; a pull-down circuit electrically coupled to the signal output terminal and a pull-down node of the shift register circuit, and configured to pull down a level at the signal output terminal under control of a level at the pull-down node; and at least one of:
a feedback circuit electrically coupled to the pull-up node, and configured to output a first feedback signal based on the level at the pull-up node; or
a pull-down control circuit electrically coupled to the pull-up node and the pull-down node, and configured to receive a second feedback signal and control the level at the pull-down node under control of the level at the pull-up node and the second feedback signal.

2 . The shift register circuit according to claim 1 , wherein the pull-down control circuit is included and comprises:
a first control sub-circuit electrically coupled to the pull-up node and the pull-down node, and configured to control the level at the pull-down node under control of the level at the pull-up node; and a second control sub-circuit electrically coupled to the first control sub-circuit, wherein the second control sub-circuit has a feedback input terminal, and is configured to receive the second feedback signal at the feedback input terminal and control turn-on and turn-off of the first control sub-circuit according to the second feedback signal.

3 . The shift register circuit according to claim 1 , wherein the feedback circuit is included and comprises:
a feedback sub-circuit electrically coupled to the pull-up node, wherein the feedback sub-circuit has a feedback output terminal, and is configured to generate the first feedback signal based on the level at the pull-up node and output the first feedback signal at the feedback output terminal; a first pull-down sub-circuit electrically coupled to the feedback sub-circuit and the pull-down node, and configured to pull down the first feedback signal generated by the feedback sub-circuit under control of the level at the pull-down node; and a second pull-down sub-circuit electrically coupled to the pull-up node and the pull-down node, and configured to pull down the level at the pull-up node under control of the level at the pull-down node.

4 . The shift register circuit according to claim 3 , wherein the feedback circuit further comprises a third pull-down sub-circuit, wherein the second pull-down sub-circuit is electrically coupled to a reference signal terminal configured to provide a reference signal through the third pull-down sub-circuit, and the third pull-down sub-circuit is electrically coupled to the pull-down node, and is configured to pull down a level at a node between the third pull-down sub-circuit and the second pull-down sub-circuit under control of the level at the pull-down node; and
the feedback output terminal is electrically coupled to the node between the third pull-down sub-circuit and the second pull-down sub-circuit.

5 . The shift register circuit according to claim 1 , wherein the shift register circuit comprises one of the feedback circuit or the pull-down control circuit, and the pull-down node comprises a first pull-down node.

6 . The shift register circuit according to claim 1 , wherein:
the shift register circuit comprises the feedback circuit and the pull-down control circuit; the pull-down node comprises a first pull-down node and a second pull-down node; the pull-down circuit is electrically coupled to the signal output terminal, the first pull-down node and the second pull-down node, and is configured to pull down the level at the signal output terminal under control of levels at the first pull-down node and the second pull-down node; and the pull-down control circuit is electrically coupled to the pull-up node and the first pull-down node, and is configured to receive the second feedback signal and control the level at the first pull-down node under control of the level at the pull-up node and the second feedback signal.

7 . The shift register circuit according to claim 6 , wherein the pull-down control circuit comprises a first control sub-circuit and a second control sub-circuit, and wherein:
the first control sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a capacitor, wherein:
the first transistor has a gate electrically coupled to a power supply signal terminal configured to provide a power supply signal, a first electrode electrically coupled to the gate, and a second electrode electrically coupled to a gate of the second transistor;
the second transistor has the gate electrically coupled to the second electrode of the first transistor, a first electrode electrically coupled to the power supply signal terminal, and a second electrode electrically coupled to the first pull-down node;
the third transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to the second electrode of the second transistor, and a second electrode electrically coupled to a reference signal terminal configured to provide a reference signal;
the fourth transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to the second electrode of the first transistor, and a second electrode electrically coupled to the reference signal terminal; and
the capacitor is electrically coupled between the gate and the second electrode of the second transistor, and
the second control sub-circuit comprises a fifth transistor, wherein the fifth transistor has a gate electrically coupled to the feedback input terminal, a first electrode electrically coupled to the second electrode of the first transistor, and a second electrode electrically coupled to the reference signal terminal.

8 . The shift register circuit according to claim 6 , wherein the feedback circuit comprises a feedback sub-circuit, a first pull-down sub-circuit, and a second pull-down sub-circuit, and wherein:
the feedback sub-circuit comprises a sixth transistor and a seventh transistor, wherein the sixth transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to a power supply signal terminal configured to provide a power supply signal, and a second electrode electrically coupled to a gate of the seventh transistor, and the seventh transistor has the gate electrically coupled to a first electrode thereof, and a second electrode electrically coupled to a feedback output terminal; the first pull-down sub-circuit comprises an eighth transistor and an eleventh transistor, wherein the eighth transistor has a gate electrically coupled to the first pull-down node, a first electrode electrically coupled to the second electrode of the sixth transistor, and a second electrode electrically coupled to a reference signal terminal configured to provide a reference signal, and the eleventh transistor has a gate electrically coupled to the second pull-down node, a first electrode electrically coupled to the second electrode of the sixth transistor, and a second electrode electrically coupled to the reference signal terminal; and the second pull-down sub-circuit comprises a ninth transistor and a twelfth transistor, wherein the ninth transistor

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yuan Can
• Li Yongqian
• Yuan Zhidong

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title