Backward compatibility through use of spoof clock and fine grain frequency control

Patent metadata

Field	Value
Publication number	US-11829197-B2
Application number	US-202117475164-A
Country	US
Kind code	B2
Filing date	Sep 14, 2021
Priority date	Feb 20, 2015
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

An application designed for the current version of a system runs at a standard clock frequency of a current version of the system. Running the application at the standard clock frequency includes synchronizing operation of a processor of the current version of the system with the standard clock frequency. An application designed for a different version of the system characterized by a different standard clock frequency runs at a second clock frequency that is different than the standard clock frequency. Running the application at the second clock frequency includes synchronizing operation of the processor of the current version of the system with the second clock frequency.

First claim

What is claimed is:

1. A method, comprising:
after it is determined whether an application loaded on a current version of a system is for the current version of the system or a less powerful version of the system,
a) running the application on a processor at a standard clock frequency of a current version of the system when the application is designed for the current version of a system, wherein running the application at the standard clock frequency includes synchronizing operation of a processor of the current version of the system with the standard clock frequency wherein the current version of the system includes a software readable cycle counter and incrementing the cycle counter at a different operating frequency than a standard clock operating frequency of a different version of the system; and
b) running the application at a second clock frequency when the application is designed for the different version of the system, wherein the different version of the system is characterized by a different standard clock frequency, wherein the second clock frequency is different than the standard clock frequency, wherein running the application at the second clock frequency includes synchronizing operation of the processor of the current version of the system with the second clock frequency and incrementing the cycle counter at the standard operating frequency of the different version of the system or a rate so close to it as to avoid triggering errors in operation.

2. The method of claim 1 , wherein the second clock frequency is higher than the different standard clock frequency.

3. The method of claim 1 , wherein b) includes setting the second frequency based on the difference in latency or latency characteristics between the current and different versions of the system, differences in throughput or speed of operation between the current and different versions of the system, or differences between the current and different versions of the system with regards to algorithms employed in computations.

4. The method of claim 1 , wherein a) includes setting the second operating frequency to different values for different applications.

5. The method of claim 1 , wherein b) includes dynamically setting the second operating frequency based on the performance characteristics of the application currently running on the processor.

6. The method of claim 1 , wherein b) further includes determining the second operating frequency by taking into account differences in latency or latency characteristics between the current version and the different version of the system.

7. The method of claim 1 , wherein b) further includes determining the second operating frequency by taking into account differences in throughput between the current version and the different version of the system.

8. The method of claim 1 , wherein b) further includes determining the second operating frequency by taking into account differences between the current version and the different version of the system with regards to algorithms used in computations.

9. The method of claim 1 , wherein the different version of the system is a less powerful system than the current version of the system.

10. The method of claim 1 , wherein the current version of the system includes a graphics processing unit (GPU) characterized by more stages in a pipeline than a GPU in the different version of the system.

11. The method of claim 1 , wherein the current version of the system includes an L3 cache and the different version of the system does not include an L3 cache.

12. The method of claim 1 , wherein the current version of the system performs processing using a different algorithm than the different version of the system.

13. The method of claim 1 , wherein the processor of the current version of the system is a central processing unit (CPU).

14. The method of claim 1 , wherein the processor of the current version of the system is a graphics processing unit (GPU).

15. A system, comprising:
a processor;
a memory; and
processor executable instructions embodied in the memory, the instructions being configured to implement a method upon execution by the processor, the method comprising:
after it is determined whether an application loaded on a current version of the system is for the current version of the system or a less powerful version of the system,
a) running the application on a processor at a standard clock frequency of a current version of the system when the application is designed for the current version of the system, wherein running the application at the standard clock frequency includes synchronizing operation of the processor with the standard clock frequency wherein the current version of the system includes a software readable cycle counter and incrementing the cycle counter at a different operating frequency than a standard operating frequency of a different version of the system; and
b) running the application at a second clock frequency when the application is designed for the different version of the system, wherein the different version of the system is characterized by a different standard clock frequency, wherein the second clock frequency is different than the standard clock frequency, wherein running the application at the second clock frequency includes synchronizing operation of the processor with the second clock frequency and incrementing the cycle counter at the standard operating frequency of the different version of the system or a rate so close to it as to avoid triggering errors in operation.

16. The system of claim 15 , wherein the second clock frequency is higher than the different standard clock frequency.

17. The system of claim 15 , wherein the second clock frequency is lower than the different standard clock frequency.

18. The system of claim 15 , wherein b) includes setting the second frequency based on the difference in latency or latency characteristics between the current and different versions of the system, differences in throughput or speed of operation between the current and different versions of the system, or differences between the current and different versions of the system with regards to algorithms employed in computations.

19. The system of claim 15 , wherein b) includes setting the second clock frequency to different values for different applications.

20. The system of claim 15 , wherein b) includes dynamically setting the second operating frequency based on the performance characteristics of the application currently running on the processor.

21. The system of claim 15 , wherein b) further includes determining the second operating frequency by taking into account differences in latency or latency characteristics between the current version and the different version of the system.

22. The system of claim 15 , wherein b) further includes determining the second operating frequency by taking into account differences in throughput between the current version and the different version of the system.

23. The system of claim 15 , wherein b) further includes determining the second operating frequency by taking into account differences between the current version and the different version of the system with regards to algorithms used in computations.

24. The system of claim 15 , wherein the different version of the system is a less powerful system than the current version of the system.

25. The system of claim 15 , wherein the current ve

Assignees

• Sony Interactive Entertainment LLC

Inventors

• Cerny Mark Evan
• Simpson David

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F15/10

  Tabulators · CPC title

• G06F15/08

  using a plugboard for programming · CPC title