Backward compatibility testing of software in a mode that disrupts timing

Patent metadata

Field	Value
Publication number	US-9892024-B2
Application number	US-201514930408-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Nov 2, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode.

First claim

What is claimed is:

1. A device, comprising:
one or more processors;
a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors, wherein the operating system is configured to selectively run in a normal mode or a timing testing mode, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors and testing the application for errors in device hardware component and/or software component synchronization while the device is running in the timing testing mode, wherein the one or more processors include one or more central processor unit (CPU) cores, wherein in the timing testing mode at least a subset of the one or more CPU cores are configured to operate at one or more frequencies that are higher than a standard operating frequency for the one or more CPU cores in the normal mode.

2. The device of claim 1 , wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application on the one or more processors by modifying one or more hardware settings of the device in real time.

3. The device of claim 1 , wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application on the one or more processors by sending commands to one or more hardware components of the device in ways that disrupt timing.

4. The device of claim 1 , wherein, in the timing testing mode, the OS modifies an operating frequency of a particular CPU core in the at least a subset of the one or more CPU cores.

5. The device of claim 1 , wherein in the timing testing mode the at least a subset of the one or more CPU cores are configured to operate at the same frequency.

6. The device of claim 1 , wherein in the timing testing mode the at least a subset of the one or more CPU cores are configured to operate at different frequencies.

7. The device of claim 1 , wherein in the timing testing mode one or more given CPU cores in the at least a subset of the one or more CPU cores is configured to operate at one frequency and one or more other CPU cores in the at least a subset of the one or more CPU cores are configured to operate at another frequency.

8. The device of claim 1 , further comprising one or more caches not contained in the one or more processors but coupled to the one or more processors, wherein in the timing testing mode at least a subset of the one or more caches are configured to operate at one or more frequencies that are different than a standard operating frequency for the one or more caches in the normal mode.

9. The device of claim 8 , wherein the at least a subset of the one or more caches are configured once to operate at one or more frequencies that are different than a standard operating frequency for the one or more caches in the normal mode.

10. The device of claim 8 , wherein, in the timing testing mode, the OS modifies an operating frequency of a cache in the at least a subset of the one or more caches.

11. The device of claim 8 , wherein in the timing testing mode the at least a subset of the one or more caches are configured to operate at the same frequency.

12. The device of claim 8 , wherein in the timing testing mode the at least a subset of the one or more caches are configured to operate at different frequencies.

13. The device of claim 8 , wherein in the timing testing mode at least one cache in the at least a subset of the one or more caches is configured to operate at one frequency and one or more other caches in the at least a subset of the one or more caches are configured to operate at another frequency.

14. The device of claim 8 , wherein one or more of the caches in the at least a subset of the one or more caches are configured to operate at one or more frequencies that are higher than a standard operating frequency for the one or more caches in the normal mode.

15. The device of claim 8 , wherein one or more of the caches in the at least a subset of the one or more caches are configured to operate at one or more frequencies that are lower than a standard operating frequency for the one or more caches in the normal mode.

16. The device of claim 1 , further comprising one or more caches coupled to the one or more processors, wherein in the timing testing mode at least a subset of the one or more caches are configured to operate with a different available way count than an available way count for the one or more caches in the normal mode.

17. The device of claim 1 , further comprising one or more caches coupled to the one or more processors, wherein in the timing testing mode at least a subset of the one or more caches are configured to operate with a different available bank count than an available bank count for the one or more caches in the normal mode.

18. The device of claim 1 , further comprising one or more caches coupled to the one or more processors, wherein at least a subset of the one or more caches that are configured to operate as inclusive caches in the normal mode are reconfigured to operate as exclusive caches in the timing testing mode.

19. The device of claim 1 , further comprising one or more caches coupled to the one or more processors, wherein at least a subset of the one or more caches that are configured to operate as exclusive caches in the normal mode are reconfigured to operate as inclusive caches in the timing testing mode.

20. The device of claim 1 , further comprising one or more caches coupled to the one or more processors, wherein a caching and cache lookup behavior for at least a subset of the one or more caches that is based on virtual addresses in the normal mode is changed to a caching and cache lookup behavior based on virtual addresses in the timing testing mode.

21. The device of claim 1 , further comprising one or more instruction caches coupled to the one or more processors, wherein a pre-fetch function for at least a subset of the one or more instruction caches that is enabled in the normal mode is disabled in the timing testing mode.

22. The device of claim 1 , wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application on the one or more processors by running one or more programs that interfere with the application.

23. The device of claim 22 , wherein the one or more programs take resources away from the application.

24. The device of claim 22 , wherein the one or more programs suspend the application.

25. The device of claim 22 , wherein the one or more programs compete for resources with the application.

26. The device of claim 1 , wherein, in the timing testing mode, the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application on the one or more processors by altering functionality of the operating system in ways that disrupt timing.

27. The device of claim 1 , wherein the one or more processors include a central processing unit (CPU), wherein, in the timing testing mode, the device is configured to disrupt timing of processing that takes

Assignees

• Sony Interactive Entertainment America Llc

Inventors

• Cerny Mark Evan
• Simpson David

Classifications

• G06F12/1045

  associated with a data cache · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F9/30079

  Pipeline control instructions, e.g. multicycle NOP · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title