Method of manufacturing a semiconductor device and a semiconductor device

Patent metadata

Field	Value
Publication number	US-11824103-B2
Application number	US-202117239225-A
Country	US
Kind code	B2
Filing date	Apr 23, 2021
Priority date	Apr 23, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure protruding from an isolation insulating layer disposed over a substrate;
forming a sacrificial gate dielectric layer over the fin structure;
forming a polysilicon layer over the sacrificial gate dielectric layer;
forming a mask pattern over the polysilicon layer; and
patterning the polysilicon layer into a sacrificial gate electrode using the mask pattern as an etching mask, wherein:
the sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, has a local minimum, and then increases from the top of the fin structure.

2. The method of claim 1 , wherein a width W1 of the sacrificial gate electrode at the level of the top of the fin structure and a width W2 of the local minimum satisfy 0.5≤W2/W1≤0.9.

3. The method of claim 1 , wherein:
the sacrificial gate electrode includes a lower portion below the level of the top of the fin structure and above an upper surface of the isolation insulating layer, and
the lower portion has an inverted spindle shape.

4. The method of claim 1 , wherein:
the patterning the polysilicon layer comprises a plasma dry etching using HBr gas and Cl 2 gas, and
a gas ratio HBr/Cl 2 is changed to form the narrow portion.

5. The method of claim 4 , wherein the gas ratio HBr/Cl 2 is reduced during the etching of the polysilicon layer.

6. The method of claim 1 further comprising:
forming gate sidewall spacers;
forming a source/drain structure including an epitaxial semiconductor layer;
forming an interlayer dielectric layer;
removing the sacrificial gate electrode and the sacrificial gate dielectric layer;
forming a gate dielectric layer and a gate electrode layer including one or more conductive material layers;
recessing the gate dielectric layer and the gate electrode layer; and
forming an insulating cap layer over the recessed gate dielectric layer and the recessed gate electrode layer.

7. The method of claim 6 , wherein a height H1 of the recessed gate electrode layer from the level of the top of the fin structure and a height H2 of the recessed gate electrode layer from the isolation insulating layer satisfy 0.1≤H1/H2≤0.7.

8. A method of manufacturing a semiconductor device, comprising:
forming a fin structure protruding from an isolation insulating layer disposed over a substrate;
forming a first sacrificial gate structure and a second sacrificial gate structure over the fin structure;
forming gate sidewall spacers on sidewalls of each of the first sacrificial gate structure and the second sacrificial gate structure;
forming an interlayer dielectric layer;
forming a first gate space by removing the first sacrificial gate structure and forming a second gate space by removing the second sacrificial gate structure;
forming a gate dielectric layer in the first and second gate space;
forming a first gate electrode layer including one or more conductive material layers over the gate dielectric layer in the first gate space and forming a second gate electrode layer including one or more conductive material layers over the gate dielectric layer in the second gate space;
recessing the gate dielectric layer and the first gate electrode layer and recessing the gate dielectric layer and the second gate electrode layer; and
forming a first insulating cap layer over the recessed gate dielectric layer and the first recessed gate electrode layer and a second insulating cap layer over the recessed gate dielectric layer and the second recessed gate electrode layer, wherein:
each of the first gate space and the second gate space has a narrow portion above a level of a top of the fin structure such that a width of each of the first and second gate spaces decreases, has a local minimum, and then increases from the top of the fin structure, and
a difference of a height of the first recessed gate electrode layer and a height of the second recessed gate electrode layer is in a range from 0.1 nm to 2 nm.

9. The method of claim 8 , wherein a number of the one or more conductive material layers of the first gate electrode is different from a number of the one or more conductive material layers of the second gate electrode.

10. The method of claim 8 , wherein the first insulating cap layer includes a portion of which width decreases toward the gate electrode layer.

11. The method of claim 8 , wherein a width W1 of the each of the first and second gate spaces at the level of the top of the fin structure and a width W2 of the local minimum satisfy 0.6≤W2/W1≤0.8.

12. The method of claim 8 , wherein:
the forming the sacrificial gate structure comprises forming a sacrificial gate electrode by patterning a polysilicon layer by using a plasma dry etching using HBr gas and Cl 2 gas, and
a gas ratio HBr/Cl 2 is changed during the plasma dry etching.

13. The method of claim 12 , wherein the gas ratio HBr/Cl 2 is reduced during etching of the polysilicon layer.

14. The method of claim 8 , wherein:
each of the first and second sacrificial gate electrodes includes a lower portion below the level of the top of the fin structure and above an upper surface of the isolation insulating layer, and
the lower portion has an inverted spindle shape.

15. A semiconductor device, comprising:
a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region;
a source/drain region disposed over the substrate;
a gate dielectric layer disposed on the channel region;
a gate electrode layer disposed on the gate dielectric layer; and
a cap insulating layer disposed on the gate electrode layer, wherein:
the gate electrode layer includes an upper portion above a level of a top of the channel region,
a width of the upper portion decreases from the top of the fin structure, and
the cap insulating layer includes a first portion having a constant width and a second portion of which width decreases toward the gate electrode layer.

16. The semiconductor device of claim 15 , wherein a width W1 of the upper portion at the level of the top of the fin structure and a width W2 of a top of the gate electrode layer satisfy 0.5≤W2/W1≤0.8.

17. The semiconductor device of claim 15 , wherein the cap insulating layer is made of SiON.

18. The semiconductor device of claim 15 , wherein the constant width of the cap insulating layer is greater than the width of the upper portion of the gate electrode layer.

19. The semiconductor device of claim 15 , further comprising gate sidewall spacers disposed on sidewall of the gate electrode layer and the cap insulating layer.

20. The semiconductor device of claim 19 , wherein a thickness along a horizontal direction of each of the gate sidewall spacers changes along a vertical direction.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Chen-Wei
• Hsueh Jen-Chih
• Chu li-feng
• Liao Chih-Teng

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10P50/268 Primary

  of silicon-containing layers · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title