Semiconductor devices including trench walls having multiple slopes

Patent metadata

Field	Value
Publication number	US-9443979-B2
Application number	US-201414455036-A
Country	US
Kind code	B2
Filing date	Aug 8, 2014
Priority date	Dec 27, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate spacer defining a trench and including a first part and a second part sequentially positioned on a substrate, an inner surface of the first part having a slope of an acute angle and an inner surface of the second part having a slope of a right angle or obtuse angle with respect to the substrate; and
a gate electrode in at least a portion of the trench.

2. The semiconductor device of claim 1 , wherein the inner surface of the first part of the gate spacer and the inner surface of the second part of the gate spacer have a continuous profile.

3. The semiconductor device of claim 1 , wherein the gate spacer further includes a third part positioned on the second part of the gate spacer remote from the first part, and the third part of the gate spacer is connected to the second part of the gate spacer.

4. The semiconductor device of claim 3 , wherein the inner surface of the second part of the gate spacer and an inner surface of the third part of the gate spacer have a discontinuous profile.

5. The semiconductor device of claim 3 , wherein at a boundary between the second part of the gate spacer and the third part of the gate spacer, a width of the trench defined by the third part of the gate spacer is greater than a width of the trench defined by the second part of the gate spacer.

6. The semiconductor device of claim 1 , wherein an inner surface of the gate spacer has a first point, a second point and a third point sequentially disposed away from the substrate, a width of the trench at the first point is greater than a width of the trench at the second point, and a width of the trench at the third point is greater than at a width of the trench at the second point.

7. The semiconductor device of claim 1 , further comprising a gate insulation film extending along side surfaces and a bottom surface of the trench between the substrate and the gate electrode,
wherein the gate electrode includes a lower gate electrode extending along the gate insulation film on the gate insulation film and an upper gate electrode on the lower gate electrode.

8. The semiconductor device of claim 1 , wherein the gate electrode is a replacement metal gate electrode.

9. The semiconductor device of claim 1 :
wherein the gate electrode includes a lower gate electrode and an upper gate electrode;
wherein the lower gate electrode extends along portions of side surfaces and a bottom surface of the trench; and
wherein the upper gate electrode is on the lower gate electrode and has a top surface coplanar with an uppermost surface of the lower gate electrode;
the semiconductor device further comprising a capping pattern on the lower gate electrode and the upper gate electrode.

10. The semiconductor device of claim 1 further comprising:
a fin type active pattern protruding onto a field insulation film;
wherein the trench extends on the fin type active pattern and crosses the fin type active pattern; and
wherein the gate electrode is a replacement metal gate electrode filling at least a portion of the trench.

11. A semiconductor device comprising:
a first gate spacer defining a first trench and including a first part and a second part sequentially positioned on a substrate, an inner surface of the first part of the first gate spacer having a slope of an acute angle and an inner surface of the second part of the first gate spacer having a slope of a right angle or obtuse angle with respect to the substrate;
a second gate spacer defining a second trench and including a third part and a fourth part sequentially positioned on the substrate, an inner surface of the third part of the second gate spacer having a slope of an acute angle and an inner surface of the fourth part of the second gate spacer having a slope of a right angle or obtuse angle with respect to the substrate;
a first gate electrode in at least a portion of the first trench and including a first n type work function control film; and
a second gate electrode in at least a portion of the second trench and including a second n type work function control film and a p type work function control film.

12. The semiconductor device of claim 11 , wherein the first gate electrode and the second gate electrode fill portions of the first trench and the second trench, respectively, and
wherein the semiconductor device further includes a first capping pattern on the first gate electrode to fill a remaining portion of the first trench, and a second capping pattern on the second gate electrode to fill a remaining portion of the second trench.

13. The semiconductor device of claim 11 , wherein the inner surface of the first part of the first gate spacer and the inner surface of the second part of the first gate spacer have a continuous profile, and the inner surface of the third part of the second gate spacer and the inner surface of the fourth part of the second gate spacer have a discontinuous profile.

14. The semiconductor device of claim 11 , wherein the first n type work function control film extends along at least portions of side surfaces and a bottom surface of the first trench, the first gate electrode includes a first filling gate electrode on the first n type work function control film to fill at least a portion of the first trench, the p type work function control film extends along at least portions of side surfaces and a bottom surface of the second trench, the second n type work function control film extends along the p type work function control film on the p type work function control film, and the second gate electrode includes a second filling gate electrode on the second n type work function control film to fill at least a portion of the second trench.

15. The semiconductor device of claim 11 , wherein the second n type work function control film extends on an uppermost surface of the p type work function control film.

16. A semiconductor device comprising:
a layer on a substrate, the layer including a trench therein that comprises a trench opening remote from the substrate, a trench floor adjacent the substrate and a trench wall between the trench opening and the trench floor, the trench wall being pinched relative to the trench opening and the trench floor, a width of a part of the trench gradually decreasing in the direction away from the substrate; and
a conductive layer in the trench that includes a conductive layer top adjacent the trench opening, a conductive layer bottom adjacent the trench floor and a conductive layer wall between the conductive layer top and the conductive layer bottom, the conductive layer wall also being pinched relative to the conductive layer top and the conductive layer bottom, a width of a part of the conductive layer gradually decreasing in the direction away from the substrate.

17. The semiconductor device of claim 16 wherein the layer comprises a gate spacer and includes first and second opposing outer walls, and the conductive layer comprise a gate electrode, the semiconductor device further comprising:
a first source/drain region on the first outer wall remote from the trench; and
a second source/drain region on the second outer wall remote from the trench.

18. The semiconductor device of claim 17 further comprising:
an active semiconductor region that extends from beneath the first source/drain region to beneath the floor of the trench and to beneath the second source/drain region.

19. The semiconductor device of claim 16 wherein the conductive layer top is recessed from the trench openin

Assignees

• Park Sang-Jine
• Yoon Bo-Un
• Jeon Ha-Young
• Cho Byung-Kwon
• Han Jeong-Nam
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Yoon Bo-Un
• Jeon Ha-Young
• Cho Byung-Kwon
• Han Jeong-Nam

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D84/834

  comprising FinFETs · CPC title