Dual-clock generation circuit and method and electronic device

Patent metadata

Field	Value
Publication number	US-11817860-B2
Application number	US-202217647885-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	Jul 14, 2021
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

First claim

The invention claimed is:

1. A dual-clock generation circuit, wherein the dual-clock generation circuit comprises:
a first inverter module, configured to access a first signal and output a first clock output signal;
a second inverter module, configured to access a second signal and output a second clock output signal, wherein the first signal and the second signal are opposite clock signals;
a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal;
a second feedforward buffer, disposed between an input terminal of the second inverter module and an output terminal of the first inverter module, and configured to transmit the second signal to delay the first clock output signal;
a first switch, disposed on a line of the first feedforward buffer, and configured to control on/off of the first feedforward buffer; and
a second switch, disposed on a line of the second feedforward buffer, and configured to control on/off of the second feedforward buffer;
wherein the first switch and the second switch respectively access a frequency control signal, to be turned on or off under control of the frequency control signal; and
wherein the first switch is configured to be turned on in response to a sampling frequency of the first signal being greater than a preset sampling rate, and the second switch is configured to be turned on in response to a sampling frequency of the second signal being greater than the preset sampling rate.

2. The circuit according to claim 1 , wherein the first switch and the second switch each are a complementary metal-oxide-semiconductor (CMOS) analog switch.

3. The circuit according to claim 1 , wherein the first feedforward buffer and the second feedforward buffer each are a complementary metal-oxide-semiconductor (CMOS) transistor comprising an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor.

4. The circuit according to claim 1 , wherein the first feedforward buffer and the second feedforward buffer each are an N-type metal-oxide-semiconductor (NMOS) transistor comprising two NMOS transistors.

5. The circuit according to claim 1 , wherein the first feedforward buffer and the second feedforward buffer each are a P-type metal-oxide-semiconductor (PMOS) transistor comprising two PMOS transistors.

6. The circuit according to claim 1 , wherein the first inverter module comprises a first inverter, and the second inverter module comprises a second inverter.

7. The circuit according to claim 6 , wherein the first inverter and the second inverter each are a complementary metal-oxide-semiconductor (CMOS) transistor comprising an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor.

8. An electronic device, wherein the electronic device comprises the dual-clock generation circuit according to claim 1 .

9. A method of generating a dual-clock, wherein the method is applied to a dual-clock generation circuit, the dual-clock generation circuit comprises a first inverter module configured to access a first signal, a second inverter module configured to access a second signal, a first feedforward buffer, and a second feedforward buffer, and the method comprises:
disposing the first feedforward buffer between an input terminal of the first inverter module and an output terminal of the second inverter module, for transmitting the first signal, to compensate for a second clock output signal output by the second inverter module;
disposing the second feedforward buffer between an input terminal of the second inverter module and an output terminal of the first inverter module, for transmitting the second signal, to delay a first clock output signal output by the first inverter module;
disposing a first switch on a line of the first feedforward buffer, for controlling on/off of the first feedforward buffer;
disposing a second switch on a line of the second feedforward buffer, for controlling on/off of the second feedforward buffer; and
connecting a frequency control signal to each of the first switch and the second switch, for controlling the first switch and the second switch to be turned on or off under control of the frequency control signal;
wherein the first switch is configured to be turned on in response to a sampling frequency of the first signal being greater than a preset sampling rate, and the second switch is configured to be turned on in response to a sampling frequency of the second signal being greater than the preset sampling rate.

10. The method according to claim 9 , wherein the method further comprises:
setting the first feedforward buffer and the second feedforward buffer to be same or different metal-oxide-semiconductor (MOS) transistors, to perform phase calibration on at least one of a rising edge of the first signal or a falling edge of the first signal.

Assignees

• Changxin Memory Tech Inc

Inventors

• Gu yinchuan

Classifications

• H03K3/356026 Primary

  with synchronous operation (H03K3/356034, H03K3/356052 take precedence) · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M1/1255

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03K5/151 Primary

  with two complementary outputs · CPC title