Semiconductor circuit

Patent metadata

Field	Value
Publication number	US-9876500-B2
Application number	US-201715499257-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Apr 28, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

First claim

What is claimed is:

1. A semiconductor circuit, comprising:
a first circuit that determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal;
a second circuit that determines a value of a second node based on a voltage level of the first node and the voltage level of the clock signal;
a third circuit that determines a value of a third node based on a voltage level of the second node; and
a fourth circuit that determines a value of a fourth node based on the voltage levels of the second node and the clock signal,
wherein the third circuit comprises a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node, and
wherein the fourth circuit comprises a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

2. The semiconductor circuit of claim 1 ,
wherein the first circuit comprises a fourth transistor that is gated to the voltage level of the clock signal to provide a power supply voltage, a fifth transistor that is connected in series with the fourth transistor and is gated to the voltage level of the enable signal to provide the power supply voltage to the first node, and a sixth transistor that is gated to the voltage level of the enable signal to provide a ground voltage to the first node.

3. The semiconductor circuit of claim 1 ,
wherein the first circuit further comprises a fourth transistor that is gated to the voltage level of the clock signal to provide a power supply voltage; a fifth transistor that is connected in series with the fourth transistor and is gated to the voltage level of the scan enable signal to provide the power supply voltage to the first node; and a sixth transistor that is gated to the voltage level of the scan enable signal to provide a ground voltage to the first node.

4. The semiconductor circuit of claim 1 ,
wherein the second circuit comprises a fourth transistor that is gated to the voltage level of the clock signal to provide a power supply voltage; a fifth transistor that is connected in parallel with the fourth transistor and is gated to a voltage level of the third node to provide the power supply voltage; a sixth transistor that is connected in series with the fourth transistor and the fifth transistor and is gated to the voltage level of the first node to provide the power supply voltage to the second node; a seventh transistor that is gated to the voltage level of the first node to provide a ground voltage to the second node; an eighth transistor that is gated to the voltage level of the third node to provide the ground voltage; and a ninth transistor that is connected in series with the eighth transistor and is gated to the voltage level of the clock signal to provide the ground voltage to the second node.

5. The semiconductor circuit of claim 4 ,
wherein, when the voltage level of the clock signal is a first logic level, the value of the second node is determined by a voltage level provided by at least one of the fourth transistor, the sixth transistor and the seventh transistor, and the value of the third node is determined by the voltage level of the second node.

6. The semiconductor circuit of claim 5 ,
wherein, when the voltage level of the clock signal transitions from the first logic level to a second logic level, the value of the second node is maintained by the voltage level of the third node, and the value of the third node is maintained by the voltage level of the second node.

7. The semiconductor circuit of claim 1 ,
wherein the fourth circuit comprises a fourth transistor that is gated to the voltage level of the second node to provide a power supply voltage to the fourth node; a fifth transistor that is connected in parallel to the fourth transistor and is gated to the voltage level of the clock signal to provide the power supply voltage to the fourth node; a sixth transistor that is gated to the voltage level of the second node to provide a ground voltage; and a seventh transistor that is connected in series with the sixth transistor to provide the ground voltage to the fourth node.

8. A semiconductor circuit, comprising:
a first node that has a logic level value different from a logic level of an enable signal or a logic level of a scan enable signal, when a clock signal is at a first logic level;
a second node in which a value is determined by the logic level of the first node when the clock signal is at the first logic level, and the value is maintained by a logic level of a third node when the clock signal is at a second logic level;
a third node in which a value is determined by the logic level of the second node; and
a fourth node in which a value is determined by the logic level of the second node when the clock signal is at the second logic level,
wherein the fourth node is discharged through a first transistor gated to a voltage level of the second node to provide a ground voltage to the fourth node, and a second transistor gated to a voltage level of the clock signal to electrically connect the third node and the fourth node.

9. The semiconductor circuit of claim 8 ,
wherein, when the enable signal or the scan enable signal is at the first logic level, the second node has the first logic level and the third node has the second logic level.

10. The semiconductor circuit of claim 9 ,
wherein the fourth node has the second logic level.

11. The semiconductor circuit of claim 8 ,
wherein, when the enable signal or the scan enable signal is at the second logic level, the second node has the second logic level and the third node has the first logic level.

12. The semiconductor circuit of claim 11 ,
wherein the third node is discharged through the first node.

13. The semiconductor circuit of claim 11 ,
wherein the fourth node has the second logic level when the clock signal is at the first logic level, and the fourth node has the first logic level when the clock signal is at the second logic level.

14. The semiconductor circuit of claim 13 ,
wherein the fourth node is discharged through the second transistor, the third node and the first node, when the clock signal is at the second logic level.

15. A semiconductor circuit, comprising:
a first logic gate that receives input of a clock signal, an enable signal or a scan enable signal and performs a first logic operation to output a first output signal to a first node;
a second logic gate that receives input of the first output signal of the first logic gate, the clock signal and a signal of a third node and performs a second logic operation to output a second output signal to a second node;
a first transistor and a second transistor that are gated to a voltage level of the second output signal of the second logic gate and connected in series with each other to determine a value of the third node;
a third logic gate that receives input of the second output signal of the second logic gate and the clock signal and performs a third logic operation to output a third output signal to a fourth node; and
a third transistor that is gated to a voltage level of the clock signal to electrically connect the third node and the fourth node.

16. The semiconductor circuit of claim 15 ,
wherein the first logic operation comprises a NOR logic operation on the clock signal, the enable signal or the scan enable signal.

17. The semiconductor circuit of claim 15 ,
whe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ah Reum
• Kim Min Su
• Kim Chung Hee
• Hwang Hyun Chul

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K3/356139 Primary

  with synchronous operation · CPC title