Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-11817482-B2
Application number	US-202016997980-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Aug 21, 2019
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A semiconductor device includes a composite layer having a first and second opposing surfaces. The composite layer includes a mesa and a first insulating layer. The mesa has top and bottom surfaces and side faces. The side faces are embedded in the first insulating layer. The mesa includes a Group III nitride-based multilayer structure providing a Group III nitride based device having first and second electrodes arranged on the mesa top surface. First and second outer contacts are positioned on the second surface of the composite layer. A first conductive via extends through the first insulating layer and is electrically coupled to the first electrode on the mesa top surface and to the first outer contact. A second conductive via extends through the first insulating layer and is electrically coupled to the second electrode on the mesa top surface and to the second outer contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a composite layer having a first surface and a second surface opposing the first surface, the composite layer comprising a mesa and a first insulating layer, the mesa having a top surface, a bottom surface and side faces, the side faces being embedded in the first insulating layer, wherein the mesa comprises a Group III nitride-based multilayer structure that provides a Group III nitride based device having a first electrode and a second electrode that are arranged on the top surface of the mesa, and the first insulating layer is formed of oxide and/or nitride material;
an insulating material positioned on the second surface of the composite layer;
a first outer contact positioned on the insulating material;
a second outer contact positioned on the insulating material;
a first conductive via extending through the first insulating layer and the insulating material, the first conductive via being electrically coupled to the first electrode on the top surface of the mesa and to the first outer contact positioned on the insulating material; and
a second conductive via extending through the first insulating layer and the insulating material, the second conductive via being electrically coupled to the second electrode on the top surface of the mesa and to the second outer contact positioned on the insulating material,
wherein the first outer contact comprises a metallic layer, one or more conductive bumps arranged on the metallic layer, and solder positioned on the conductive bumps.

2. The semiconductor device of claim 1 , wherein the mesa further comprises a foreign base substrate, the foreign base substrate having an upper surface capable of supporting epitaxial growth of at least one Group III nitride and a lower surface forming the bottom surface of the mesa, wherein the Group III nitride-based multilayer structure is epitaxially formed on the upper surface of the foreign base substrate.

3. The semiconductor device of claim 2 , wherein the foreign base substrate has a thickness a thickness t, wherein the Group III nitride-based multilayer structure has a thickness t n , and wherein t≤t n and 0 μm≤t≤20 μm, or 0≤t≤5 μm or 0.1 μm≤t≤2 μm or 1 μm≤t≤2 μm.

4. The semiconductor device of claim 1 , wherein the first surface of the composite layer comprises the top surface of the mesa and a top surface of the first insulating layer, and wherein the second surface of the composite layer comprises the bottom surface of the mesa and a bottom surface of the first insulating layer.

5. The semiconductor device of claim 1 , wherein the Group III nitride based device is a transistor device comprising a source electrode, a drain electrode and a gate electrode, wherein the first electrode provides the source electrode, and wherein the second electrode provides the drain electrode.

6. The semiconductor device of claim 5 , further comprising a third conductive via positioned in the first insulating layer, wherein the third conductive via is coupled to the gate electrode and to a third outer contact positioned on the second surface of the composite layer.

7. The semiconductor device of claim 1 , further comprising a first conductive redistribution layer arranged on the first surface of the composite layer, wherein the first conductive redistribution layer comprises:
a second insulating layer on the first surface of the composite layer;
a first lateral conductive redistribution structure on the second insulating layer;
a fourth conductive via extending through the second insulating layer that electrically couples the first electrode of the Group III nitride-based device to the first lateral conductive redistribution structure; and
a fifth conductive via that electrically couples the first lateral conductive redistribution structure to the first conductive via.

8. The semiconductor device of claim 1 , wherein the first outer contact extends over the bottom surface of the mesa.

9. The semiconductor device of claim 1 , further comprising a semiconductor wafer arranged on the first surface of the composite layer.

10. The semiconductor device of claim 9 , wherein the semiconductor wafer comprises at least one semiconductor device and a redistribution structure that is electrically coupled to the semiconductor device, and wherein the semiconductor device is a CMOS device, or a bipolar device, or a passive device, or passive devices for impedance matching, or active devices as a pre-driver, a low noise amplifier or full receive path or CMOS logic for digital signal processing.

11. The semiconductor device of claim 1 , further comprising a parasitic channel suppression region positioned at the interface between the side faces of the mesa and the first insulating layer and/or in the mesa and/or at the bottom surface of the mesa, wherein the parasitic channel suppression region comprises an amorphous layer or a polycrystalline layer or a high-defect density region.

12. The semiconductor device of claim 11 , wherein the parasitic channel suppression region further comprises implanted species, and wherein the implanted species comprise at least one selected from the group consisting of Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si and Al.

13. The semiconductor device of claim 1 , wherein the first electrode on the top surface of the mesa and the first outer contact positioned on the insulating material are at a same first potential, wherein the second electrode on the top surface of the mesa and the second outer contact positioned on the insulating material are at a same second potential, and wherein the first potential is different than the second potential.

Assignees

• Infineon Technologies Ag

Inventors

• Brech Helmut
• Ahrens Carsten
• Zigldrum Matthias

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title