Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9929107-B1
Application number	US-201615370536-A
Country	US
Kind code	B1
Filing date	Dec 6, 2016
Priority date	Dec 6, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

In an embodiment, a method includes forming an opening in a front surface of a substrate including at least one Group III nitride-based transistor on the first surface, inserting conductive material into the opening, and coupling a source electrode of the Group III nitride-based transistor to a rear surface of the substrate with the conductive material.

First claim

What is claimed is:

1. A method, comprising:
forming an opening in a front surface of a substrate comprising at least one Group III nitride-based transistor on the front surface;
inserting conductive material into the opening; and
coupling a source electrode of the Group III nitride-based transistor to a rear surface of the substrate with the conductive material,
epitaxially depositing a first Group III nitride layer having a first bandgap on the front surface of the substrate;
epitaxially depositing a second Group III nitride layer having a second bandgap different from the first bandgap on the front surface of the substrate so as to form a heterojunction between the first Group III nitride layer and the second Group III nitride layer;
forming a metallization structure on the second Group III nitride layer so as to form a transistor structure; and
inserting the opening through the first Group III nitride layer and the second Group III nitride layer and into the front surface of the substrate.

2. The method of claim 1 , wherein the opening is a blind via, the conductive material is inserted into the blind via and material is removed from the rear surface of the substrate to expose a surface of the conductive material and produce a conductive through substrate via.

3. The method of claim 1 , wherein the Group III nitride based transistor is formed in a mesa arranged on the front surface of the substrate, the mesa comprising a first epitaxial Group III nitride layer having a first bandgap and a second epitaxial Group III nitride layer having a second bandgap different from the first bandgap with a heterojunction therebetween, wherein the mesa is embedded in an insulation layer arranged on the front surface of the substrate, and wherein the opening is inserted through the insulation layer and into the front surface of the substrate.

4. The method of claim 1 , further comprising:
applying a metallization structure to the front surface of the substrate;
removing material from the rear surface of the substrate so as to expose a surface of the conductive material; and
applying a conductive layer to the rear surface.

5. The method of claim 1 , further comprising forming the conductive material on the front surface of the substrate adjacent the opening.

6. The method of claim 5 , further comprising forming the conductive material on a conductive layer arranged on the front surface that is electrically coupled with a source electrode of the Group III nitride-based transistor.

7. The method of claim 1 , wherein inserting the conductive material into the opening comprises substantially filling the opening with the conductive material.

8. The method of claim 7 , wherein the conductive material is inserted by electroplating.

9. A method, comprising:
forming an opening in a front surface of a substrate comprising at least one Group III nitride-based transistor on the front surface;
inserting conductive material into the opening; and
coupling a source electrode of the Group III nitride-based transistor to a rear surface of the substrate with the conductive material,
wherein inserting the conductive material into the opening comprises:
forming a first conductive layer in a first portion of the opening in the substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion; and
forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

10. The method of claim 9 , wherein the first deposition parameters are selected so as to favour growth of the first conductive layer in a vertical direction with respect to a major surface of the substrate and the second deposition parameters are selected so as to favour growth of the second conductive layer in a lateral direction with respect to the major surface of the substrate.

11. The method of claim 9 , wherein the first conductive layer and the second conductive layer are formed by electroplating.

12. The method of claim 9 , wherein the opening is a blind via, the first conductive layer is applied to a base of the blind via and the base of the blind via is filled with the first conductive layer.

13. The method of claim 12 , wherein the first conductive layer fills the blind via to a depth of 10% to 70% of a total depth of the blind via.

14. The method of claim 9 , further comprising:
after applying the second conductive layer, capping the gap in the second portion of the opening.

15. The method of claim 9 , further comprising forming a first insulation layer over the second conductive layer that surrounds a gap and forming a second insulation layer over the gap so as to form an enclosed cavity within the opening.

16. The method of claim 9 , wherein the opening is a blind via, the conductive material is inserted into the blind via and material is removed from the rear surface of the substrate to expose a surface of the conductive material and produce a conductive through substrate via.

17. The method of claim 9 , further comprising:
epitaxially depositing a first Group III nitride layer having a first bandgap on the front surface of the substrate;
epitaxially depositing a second Group III nitride layer having a second bandgap different from the first bandgap on the front surface of the substrate so as to form a heterojunction between the first Group III nitride layer and the second Group III nitride layer;
forming a metallization structure on the second Group III nitride layer so as to form a transistor structure; and
inserting the opening through the first Group III nitride layer and the second Group III nitride layer and into the front surface of the substrate.

18. The method of claim 9 , wherein the Group III nitride based transistor is formed in a mesa arranged on the front surface of the substrate, the mesa comprising a first epitaxial Group III nitride layer having a first bandgap and a second epitaxial Group III nitride layer having a second bandgap different from the first bandgap with a heterojunction therebetween, wherein the mesa is embedded in an insulation layer arranged on the front surface of the substrate, and wherein the opening is inserted through the insulation layer and into the front surface of the substrate.

19. The method of claim 9 , further comprising:
applying a metallization structure to the front surface of the substrate;
removing material from the rear surface of the substrate so as to expose a surface of the conductive material; and
applying a conductive layer to the rear surface.

20. The method of claim 9 , further comprising forming the conductive material on the front surface of the substrate adjacent the opening.

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title