Display driving circuit

Patent metadata

Field	Value
Publication number	US-11817067-B2
Application number	US-202117221461-A
Country	US
Kind code	B2
Filing date	Apr 2, 2021
Priority date	Apr 14, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A display driving circuit for driving a display panel, including a first memory configured to store main image data received from outside of the display driving circuit; a second memory configured to store first additional image data in a normal mode, and to store second additional image data in an Always On Display (AOD) mode having lower power consumption than the normal mode; a normal mode controller configured to operate in the normal mode according to the first additional image data stored in the second memory; and an AOD mode controller configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory.

First claim

What is claimed is:

1. A display driving circuit for driving a display panel, the display driving circuit comprising:
a first memory configured to store main image data received from outside of the display driving circuit, wherein the main image data corresponds to a background image;
a second memory configured to store first additional image data in a normal mode, and to store second additional image data in an Always On Display (AOD) mode having lower power consumption than the normal mode;
a normal mode controller configured to operate in the normal mode according to the first additional image data stored in the second memory; and
an AOD mode controller configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory,
wherein the main image data is stored in a compressed form in the first memory, and is decompressed by the display driving circuit before being used, and wherein at least one of the first additional image data and the second additional image data is stored in an uncompressed form in the second memory, and is not decompressed by the display driving circuit before being used.

2. The display driving circuit of claim 1 , further comprising an internal time information generation circuit configured to receive a clock signal and time information, and to generate internal time information based on the clock signal and the time information,
wherein the AOD mode controller operates in the AOD mode based on the internal time information.

3. The display driving circuit of claim 2 , wherein the clock signal is received from the outside of the display driving circuit.

4. The display driving circuit of claim 1 , further comprising a distributor configured to:
receive the first additional image data and the second additional image data from the second memory;
transmit the first additional image data to the normal mode controller according to a mode selection signal; and
transmit the second additional image data to the AOD mode controller according to the mode selection signal.

5. The display driving circuit of claim 1 , further comprising a decoder configured to:
receive the main image data from the first memory;
decode the received main image data; and
transmit the decoded main image data to the AOD mode controller.

6. The display driving circuit of claim 1 , wherein the normal mode controller does not operate in the AOD mode, and
wherein the AOD mode controller does not operate in the normal mode.

7. The display driving circuit of claim 1 , wherein the first memory includes graphic random access memory (RAM), and the second memory includes static RAM (SRAM).

8. A display driving circuit for driving a display panel, the display driving circuit comprising:
a first memory configured to store first main image data in a normal mode and second main image data in an Always On Display (AOD) mode having lower power consumption than the normal mode;
a distributor configured to receive the first main image data and the second main image data from the first memory, and distribute the first main image data and the second main image data according to a mode selection signal;
a decoder configured to receive the first main image data from the distributor and decode the received first main image data, and generate the decoded first main image data;
a normal mode controller configured to operate in the normal mode according to the decoded first main image data; and
an AOD mode controller configured to receive the second main image data from the distributor without the second main image data passing through the decoder, and to operate in the AOD mode according to the second main image data.

9. The display driving circuit of claim 8 , further comprising a second memory configured to store first additional image data in the AOD mode,
wherein the AOD mode controller is further configured to operate in the AOD mode according to the second main image data and the first additional image data.

10. The display driving circuit of claim 9 , wherein the second memory is further configured to store second additional image data in the normal mode,
wherein the normal mode controller is further configured to operate in the normal mode according to the decoded first main image data and the second additional image data.

11. The display driving circuit of claim 8 , further comprising:
an oscillator configured to generate a clock signal; and
an internal time information generation circuit configured to generate internal time information based on the clock signal and time information received from outside of the display driving circuit,
wherein the AOD mode controller is further configured to operate in the AOD mode based on the internal time information.

12. The display driving circuit of claim 8 , further comprising an internal time information generation circuit configured to generate internal time information based on a clock signal received from outside of the display driving circuit and time information received from the outside,
wherein the AOD mode controller is further configured to operate in the AOD mode based on the internal time information.

13. A display driving circuit for driving a display panel, the display driving circuit comprising:
a first memory configured to store merged image data received from outside of the display driving circuit;
an image modification circuit configured to extract additional image data from a data area of the merged image data, and to generate main image data by setting a portion of a main image corresponding to the data area to be displayed as a black area;
an internal time information generation circuit configured to generate internal time information based on a clock signal and time information; and
an Always On Display (AOD) mode controller configured to operate in an AOD mode having lower power consumption than a normal mode according to the main image data, the additional image data, and the internal time information
wherein the image modification circuit is further configured to extract the additional image data from the merged image data based on an address which indicates a position of the additional image data within the main image data.

14. The display driving circuit of claim 13 , further comprising a decoder configured to:
receive the merged image data from the first memory;
decode the received merged image data; and
transmit the decoded merged image data to the image modification circuit,
wherein the image modification circuit is further configured to extract the additional image data from the decoded merged image data.

15. The display driving circuit of claim 13 , further comprising a second memory configured to:
receive the additional image data from the image modification circuit;
store the received additional image data; and
provide the additional image data to the AOD mode controller.

16. The display driving circuit of claim 13 , further comprising a decoder configured to:
receive the main image data from the image modification circuit;
decode the received main image data; and
transmit the decoded main image data to the AOD mode controller.

17. The display driving circuit of claim 13 , wherein the clock signal is received from the outside.

18. The display driving circuit of claim 13 , wherein the address is received from the outside.

19. The display driving circuit of claim 13 , wherein the address is pre-stored in the image modification circuit, and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Unki
• Kim Minsik
• Park Hyeonsu
• Lee Jonghyuk
• Lim Hyunwook
• Jang Woohyuk

Classifications

• G09G5/393 Primary

  Arrangements for updating the contents of the bit-mapped memory · CPC title

• G04G9/0082

  by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08 · CPC title

• G09G5/395

  Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2360/06

  Use of more than one graphics processor to process data before displaying to one or more screens · CPC title