Method for processing image and electronic device supporting the same

US10467951B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10467951-B2
Application numberUS-201715690500-A
CountryUS
Kind codeB2
Filing dateAug 30, 2017
Priority dateAug 30, 2016
Publication dateNov 5, 2019
Grant dateNov 5, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes a display panel that outputs content through a plurality of pixels, a display driver integrated circuit configured to transmit a driving signal for driving the display panel, and a processor configured to transmit image data and/or a control signal to the display driver integrated circuit. In the case where the display driver integrated circuit receives first image data transmitted together with a command of a first command group from the processor, the display driver integrated circuit is configured to store the first image data in a first memory area. In the case where the display driver integrated circuit receives second image data transmitted together with a command of a second command group from the processor, the display driver integrated circuit is configured to store the second image data in a second memory area different from the first memory area.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a display panel configured to output content through a plurality of pixels; a display driver integrated circuit comprising a plurality of logic circuits configured at least to transmit a driving signal for driving the display panel; and at least one processor configured to transmit image data and a control signal to the display driver integrated circuit, wherein, in the case where the display driver integrated circuit receives first image data and a first control signal related to the first image data from the processor, the display driver integrated circuit is configured to store the first image data in a first memory area of the display driver integrated circuit, wherein, in the case where the display driver integrated circuit receives second image data and a second control signal related to the second image data from the processor, the display driver integrated circuit is configured to store the second image data in a second memory area of the display driver integrated circuit, wherein a portion of the plurality of logic circuits of the display driver integrated circuit is configured to combine the first image data from the first memory area with the second image data from the second memory area, and output the combined image data to the display panel while the processor is in sleep state, and wherein the first image data to be combined is maintained and the second image data to be combined is to be periodically modified by the display driver integrated circuit depending on at least one of a specified time period and a specified event while the processor is in sleep state. 2. The electronic device of claim 1 , wherein the display driver integrated circuit is configured to operate the display panel based on the first and second image data stored in the first memory area and the second memory area, respectively, while the processor is deactivated. 3. The electronic device of claim 1 , wherein the object includes at least one of: a hand of an analog clock, a number or a division sign of a digital clock, an icon, a mouse pointer, or a touch pointer. 4. The electronic device of claim 1 , wherein the display driver integrated circuit is configured to output first image data to a first layer of the display panel, and wherein the second image data is usable to generate an object to be output to a second layer of the display panel overlaid on the first layer. 5. The electronic device of claim 1 , wherein the first control signal includes a recording start command usable to start recording data in the first memory area, and a recording continuousness command usable to continuously record the data in the first memory area. 6. The electronic device of claim 5 , wherein the recording start command includes image data combined with a 2Ch command according to a mobile industry processor interface (MIPI) standard, and wherein the recording continuousness command includes image data combined with a 3Ch command according to the MIPI standard. 7. The electronic device of claim 1 , wherein the second control signal includes a recording start command usable to start recording data in the second memory area, and a recording continuousness command usable to continuously record the data in the second memory area. 8. The electronic device of claim 7 , wherein the recording start command of the second control signal includes one or two of commands from 00h to FFh other than a 2Ch command and a 3Ch command according to a mobile industry processor interface (MIPI) standard, and wherein the recording continuousness command of the second control signal includes one or two of commands from 00h to FFh other than the 2Ch command, the 3Ch command, and a command allocated to the recording start command. 9. The electronic device of claim 1 , wherein the first memory area and the second memory area are provided in different areas in one graphics random access memory (RAM), or are implemented with graphics RAMs physically independent of each other. 10. The electronic device of claim 1 , wherein the processor is configured to generate additional information based on transparency of each of the pixels, to generate conversion data that includes the additional information, the conversion data being smaller in size than base data of the pixels, and to transmit the conversion data to the display driver integrated circuit, and wherein the display driver integrated circuit is configured to store the conversion data in the second memory area as the second image data. 11. The electronic device of claim 10 , wherein the conversion data includes a red (R) component, a green (G) component, and a blue (B) component of each of the pixels and the additional information, and wherein the display driver integrated circuit is configured to display the red (R) component with a first number of levels, to display the green (G) component with a second number of levels, to display the blue (B) component with a third number of levels, and to display the additional information with a fourth number of levels. 12. The electronic device of claim 11 , wherein a sum of the first number, the second number, the third number and the fourth number is less than a sum of bits of the transparency, the red (R) component, the green (G) component, and the blue (B) component of each pixel, which are included in the base data. 13. The electronic device of claim 11 , wherein a sum of the first number, the second number, the third number and the fourth number is equal to a value of a bit width allocated to each pixel of the display panel. 14. The electronic device of claim 10 , wherein the additional information includes at least one of: transparency information of each pixel, and information on whether each pixel is disposed in an edge area where the transparency is changed by a specified value or more. 15. The electronic device of claim 10 , wherein the processor is configured to transmit conversion data to the display driver integrated circuit, together with a display driving command or image data transmitted to the display panel. 16. The electronic device of claim 15 , wherein the display driving command has a bus width of a 8-bit unit for one command, and wherein the conversion data is configured to be transmitted having a parameter of 256 bytes or more in one command. 17. A method for processing an image, performed in an electronic device including a display, the method comprising: generating, at a processor, first image data; transmitting, at the processor, the first image data and a first control signal to the first image data to a display driver integrated circuit driving the display; storing, at the display driver integrated circuit, the first image data in a first memory area of the display driver integrated circuit; generating, at the processor, second image; transmitting, at the processor, the second image data and a second control signal related to the second image data to the display driver integrated circuit; storing, at the display driver integrated circuit, the second image data in a second memory area of the display driver integrated circuit, the second memory area being different than the first memory area; combining, at the display driver integrated circuit, the first image data from the first memory area with the second image data from the second memory area, and outputting the combined image data to the display while the processor is in sleep state, wherein the first image data to be combined is maintained and the second image data to be combined is periodicall

Assignees

Inventors

Classifications

  • Handling of images in compressed format, e.g. JPEG, MPEG · CPC title

  • Centralised management of display operation, e.g. in a server instead of locally · CPC title

  • Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title

  • Details of image data interface between the display device controller and the data line driver circuit · CPC title

  • Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

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What does patent US10467951B2 cover?
An electronic device includes a display panel that outputs content through a plurality of pixels, a display driver integrated circuit configured to transmit a driving signal for driving the display panel, and a processor configured to transmit image data and/or a control signal to the display driver integrated circuit. In the case where the display driver integrated circuit receives first image…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/2096. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).