Methods for row hammer mitigation and memory devices and systems employing the same

Patent metadata

Field	Value
Publication number	US-11810610-B2
Application number	US-202117387934-A
Country	US
Kind code	B2
Filing date	Jul 28, 2021
Priority date	Oct 9, 2018
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

First claim

What is claimed is:

1. A method, comprising:
determining a count corresponding to a number of activations at a memory location of a memory device;
issuing a command to execute a first refresh management operation for the memory location in response to the count exceeding a first predetermined threshold;
decreasing the count by an amount that is less than the count;
issuing, before the execution of the first refresh management operation, a command to perform a second refresh management operation; and
decreasing the count by the amount in response to executing the second refresh management operation.

2. The method of claim 1 , further comprising:
disallowing, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

3. The method of claim 1 , wherein the memory location comprises a memory bank.

4. The method of claim 3 , wherein the first refresh management operation comprises refreshing a subset of a plurality of rows of the memory bank.

5. The method of claim 1 , wherein the amount is a first amount, and further comprising:
decreasing the count by a second amount in response to executing a periodic refresh operation at the memory location.

6. The method of claim 5 , wherein the periodic refresh operation comprises refreshing only a single memory bank including the memory location.

7. The method of claim 5 , wherein the periodic refresh operation comprises refreshing a plurality of memory banks of the memory device.

8. The method of claim 1 , wherein the memory location comprises a subset of a plurality of rows of the memory device.

9. An apparatus, comprising:
a memory including a memory location; and
circuitry configured to:
determine a count corresponding to a number of activations at the memory location;
issue a command to execute a first refresh management operation for the memory location in response to the count exceeding a first predetermined threshold;
decrease the count by an amount that is less than the count;
issue, before the execution of the first refresh management operation, a command to perform a second refresh management operation; and
decrease the count by the amount in response to executing the second refresh management operation.

10. The apparatus of claim 9 , wherein the circuitry is further configured to:
disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

11. The apparatus of claim 9 , wherein the memory location comprises a memory bank.

12. The apparatus of claim 11 , wherein the first refresh management operation comprises refreshing a subset of a plurality of rows of the memory bank impacted by the activations.

13. The apparatus of claim 9 , wherein the amount is a first amount, and wherein the circuitry is further configured to:
decrease the count by a second amount in response to executing a periodic refresh operation at the memory location.

14. The apparatus of claim 13 , wherein the periodic refresh operation comprises refreshing only a single memory bank including the memory location.

15. The apparatus of claim 13 , wherein the periodic refresh operation comprises refreshing a plurality of memory banks of the memory device.

16. The apparatus of claim 9 , wherein the memory comprises a dynamic random access memory (DRAM) device.

17. An apparatus, comprising:
a memory including a memory location; and
circuitry configured to:
determine a count corresponding to a number of activations at the memory location;
issue a command to refresh the memory location after the count exceeds a first predetermined threshold;
decrease the count by an amount that is less than the count; and
disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

18. The apparatus of claim 17 , wherein the amount is a multiple of the first predetermined threshold, and wherein the multiple is one of 0.5 and 1.0.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Cowles Timothy B
• Gans Dean D
• Li Jiyun
• Meier Nathaniel J
• Rooney Randall J

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title