Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control

Patent metadata

Field	Value
Publication number	US-11804470-B2
Application number	US-201916548255-A
Country	US
Kind code	B2
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a plurality of first dies on a substrate;
an encapsulation layer over the substrate, wherein the encapsulation layer surrounds the plurality of first dies;
an interface layer over the plurality of first dies and the encapsulation layer, wherein the interface layer has a portion with a bottom having a curved surface; and
a passive heat spreader on the interface layer, wherein the interface layer thermally couples the plurality of first dies to the passive heat spreader.

2. The semiconductor package of claim 1 , wherein the passive heat spreader includes a silicon (Si) material or a silicon carbide (SiC) material.

3. The semiconductor package of claim 1 , wherein the interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material.

4. The semiconductor package of claim 1 , wherein the interface layer has a first thickness and a second thickness, wherein the first thickness of the interface layer is less than the second thickness of the interface layer.

5. The semiconductor package of claim 1 , wherein the substrate includes a plurality of through silicon vias (TSVs).

6. The semiconductor package of claim 5 , further comprising:
a plurality of second dies on a package substrate, wherein the substrate is on the package substrate, wherein the plurality of second dies have top surfaces that are substantially coplanar to a top surface of the passive heat spreader, wherein the plurality of second dies are adjacent to outer edges of the passive heat spreader and the substrate, and wherein the plurality of TSVs of the substrate conductively couple the plurality of first dies to the package substrate;
a thermal interface material (TIM) over the plurality of second dies, the passive heat spreader, and the package substrate, wherein the TIM has a thickness above the plurality of second dies that is substantially equal to a thickness of the TIM above the passive heat spreader, wherein the TIM has a bottom surface that is directly on the top surfaces of the plurality of second dies and the passive heat spreader, and wherein the bottom surface of the TIM is substantially coplanar to the top surfaces of the plurality of second dies and the top surface of the passive heat spreader;
a heat spreader over the TIM and the package substrate, wherein the heat spreader includes a lid and a plurality of legs, wherein the lid of the heat spreader is directly on a top surface of the TIM, and wherein the plurality of legs of the heat spreader are directly on a top surface of the package substrate; and
an underfill material on the top surface of the package substrate, wherein the underfill material surrounds portions of the plurality of second dies, the encapsulation layer, and the substrate.

7. The semiconductor package of claim 6 , wherein the plurality of first dies has a first thickness that is less than a second thickness of the plurality of second dies, wherein the passive heat spreader has a thickness that is greater than the first thickness of the plurality of first dies, wherein the second thickness of the plurality of second dies is substantially equal to a combined thickness of the passive heat spreader, the plurality of first dies, and the substrate, wherein the TIM has a single monolithic thickness, and wherein the lid of the heat spreader has a single monolithic thickness.

8. The semiconductor package of claim 6 , wherein the plurality of second dies include a high-bandwidth memory (HBM) die.

9. The semiconductor package of claim 6 , wherein the TIM is a solder TIM (STIM), and wherein the passive heat spreader is coupled to the TIM with a backside metallization (BSM) layer.

10. A semiconductor package, comprising:
a plurality of substrates on a package substrate;
a plurality of first dies on the plurality of substrates;
a plurality of second dies on the package substrate;
an encapsulation layer over the plurality of substrates, wherein the encapsulation layer surrounds the plurality of first dies;
a plurality of interface layers over the plurality of first dies and the encapsulation layer;
a plurality of passive heat spreaders on the plurality of interface layers, wherein the plurality of interface layers thermally couples the respective plurality of first dies to the respective to plurality of passive heat spreaders, wherein the plurality of second dies are adjacent to outer edges of the plurality of passive heat spreaders and the plurality of substrates, and wherein the plurality of second dies have top surfaces that are substantially coplanar to top surfaces of the plurality of passive heat spreaders;
a TIM over the plurality of second dies, the plurality of passive heat spreaders, and the package substrate; and
a heat spreader over the TIM and the package substrate.

11. The semiconductor package of claim 10 , wherein the passive heat spreader includes a Si or a SiC, and wherein the interface layer includes a SiN material, a SiO material, a SiCN material, or a thermal adhesive material.

12. The semiconductor package of claim 11 , wherein the interface layer has a third thickness and a fourth thickness, wherein the third thickness of the interface layer is less than the fourth thickness of the interface layer, wherein the interface layer has a bottom surface, and wherein the bottom surface of the interface layer has a portion with a curved surface.

13. The semiconductor package of claim 11 , wherein the plurality of substrates include a plurality of TSVs, and wherein the plurality of TSVs of the plurality of substrates conductively couple the plurality of first dies to the package substrate.

14. The semiconductor package of claim 10 , further comprising an underfill material on a top surface of the package substrate, wherein the underfill material surrounds portions of the plurality of second dies, the encapsulation layer, and the plurality of substrates, wherein the TIM has a thickness above the plurality of second dies that is substantially equal to a thickness of the TIM above the plurality of passive heat spreaders, wherein the TIM has a bottom surface that is directly on the top surfaces of the plurality of second dies and the plurality of passive heat spreaders, and wherein the bottom surface of the TIM is substantially coplanar to the top surfaces of the plurality of second dies and the top surfaces of the plurality of passive heat spreaders, wherein the heat spreader includes a lid and a plurality of legs, wherein the lid of the heat spreader is directly on a top surface of the TIM, and wherein the plurality of legs of the heat spreader are directly on the top surface of the package substrate.

15. The semiconductor package of claim 14 , wherein the plurality of first dies have a first thickness that is less than a second thickness of the plurality of second dies, wherein the plurality of passive heat spreaders have a thickness that is greater than the first thickness of the plurality of first dies, wherein the second thickness of the plurality of second dies is substantially equal to a combined thickness of the plurality of passive heat spreaders, the plurality of first dies, and the plurality of substrates, wherein the TIM has a single monolithic thickness, and wherein the lid of the heat spreader has a single monolithic thickness.

16. The semiconductor package of claim 14 , wherein the plurality of second dies include a HBM die, wherein the TIM is a STIM, and wherein the plurality of passive heat spreaders are coupled to the TIM with a p

Assignees

• Intel Corp

Inventors

• Brun Xavier F
• Mistry Kaizad
• Start Paul R
• Ananthakrishnan Nisha
• Liang Yawei
• Patel Jigneshkumar P
• Agraharam Sairam
• Wang Liwei

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/353

  not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title