Semiconductor devices comprising electrical redistribution layer along with ground line and signal line and methods for manufacturing thereof

Patent metadata

Field	Value
Publication number	US-11798874-B2
Application number	US-202117456806-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Dec 8, 2020
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A semiconductor device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip, an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board, and an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element. The electrical redistribution layer includes a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor chip comprising an electrical contact arranged on a main surface of the semiconductor chip;
an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board; and
an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element,
wherein the electrical redistribution layer comprises a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength,
wherein, when viewed in a direction perpendicular to the main surface of the semiconductor chip:
a width of a gap between the ground line and the signal line is continuously smaller than 10 percent of the wavelength and at least smaller than 40 micrometers along a path,
a variation of the width of the gap is continuously smaller than 25 percent of the width of the gap along the path,
a starting point of the path and the electrical contact of the semiconductor chip have a similar coordinate with respect to a coordinate axis in a direction from the electrical contact to a center of the external connection element, and
an end point of the path and the center of the external connection element have a similar coordinate with respect to the coordinate axis in the direction from the electrical contact to the center of the external connection element.

2. The semiconductor device of claim 1 , wherein the width of the gap between the ground line and the signal line is continuously smaller than 5 percent of the wavelength along the path.

3. The semiconductor device of claim 1 , wherein the starting point of the path and a center of the electrical contact of the semiconductor chip have a similar coordinate with respect to the coordinate axis in the direction from the electrical contact to the center of the external connection element.

4. The semiconductor device of claim 1 , wherein the width of the gap is continuously smaller than 40 micrometers along the path.

5. The semiconductor device of claim 1 , wherein the ground line and the signal line form a coplanar waveguide.

6. The semiconductor device of claim 1 , further comprising:
an encapsulation material, wherein the semiconductor chip is at least partly embedded in the encapsulation material, wherein the main surface of the semiconductor chip and a main surface of the encapsulation material are arranged in a common plane, wherein the electrical redistribution layer is at least partly extending over the main surface of the encapsulation material, and wherein the external connection element is arranged lateral to the semiconductor chip.

7. The semiconductor device of claim 1 , wherein the semiconductor device comprises an embedded wafer level ball grid array package.

8. The semiconductor device of claim 1 , wherein the external connection element is arranged based on a ball grid array having a ball pitch, wherein the signal line has a length of at least twice the ball pitch.

9. The semiconductor device of claim 1 , wherein a distance between an end point of the signal line and an edge of the semiconductor chip equals a distance between an end point of the ground line and the edge of the semiconductor chip.

10. The semiconductor device of claim 1 , wherein a distance between an end point of the signal line and an edge of the semiconductor chip is greater than one or more of a thickness of the semiconductor chip or a diameter of the external connection element.

11. The semiconductor device of claim 1 , wherein the ground line and the signal line at least partly extend in a parallel direction.

12. The semiconductor device of claim 1 , wherein a distance between the ground line and the signal line increases in a direction pointing away from an edge of the semiconductor chip.

13. The semiconductor device of claim 1 , wherein the electrical redistribution layer comprises a cheesing pattern.

14. The semiconductor device of claim 1 , further comprising:
a further ground line connected to a ground potential, wherein the signal line is arranged between the ground line and the further ground line.

15. The semiconductor device of claim 1 , wherein the external connection element is configured to provide a mechanical connection between the semiconductor device and the printed circuit board.

16. A semiconductor device, comprising:
a semiconductor chip comprising an electrical contact arranged on a main surface of the semiconductor chip;
an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board; and
an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element,
wherein the electrical redistribution layer comprises a ground line connected to a ground potential and a signal line configured to carry an electrical signal,
wherein, when viewed in a direction perpendicular to the main surface of the semiconductor chip:
a variation of a width of a gap between the ground line and the signal line is continuously smaller than 25 percent of the width of the gap along a path,
a starting point of the path and the electrical contact of the semiconductor chip have a similar coordinate with respect to a coordinate axis in a direction from the electrical contact to a center of the external connection element, and
an end point of the path and the center of the external connection element have a similar coordinate with respect to the coordinate axis in the direction from the electrical contact to the center of the external connection element.

17. The semiconductor device of claim 16 , wherein the starting point of the path and the center of the electrical contact of the semiconductor chip have a similar coordinate with respect to the coordinate axis in the direction from the electrical contact to the center of the external connection element.

18. The semiconductor device of claim 16 , wherein:
the signal line is associated with a first RF channel, and
an electromagnetic isolation between the signal line and a further signal line, arranged adjacent to the signal line and associated with a second RF channel, is more than 30 dB.

19. The semiconductor device of claim 18 , wherein a distance between the signal line and the further signal line is smaller than 3.5 mm.

20. A method for manufacturing a semiconductor device, wherein the method comprises:
generating a semiconductor chip comprising an electrical contact arranged on a main surface of the semiconductor chip;
fabricating an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board; and
fabricating an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element,
wherein the electrical redistribution layer comprises a ground line connected to a ground potential and a signal line configured to carry an electrical signal

Assignees

• Infineon Technologies Ag

Inventors

• Hartner Walter
• Arcioni Francesca
• Erdoel Tuncay
• Fiore Vincenzo
• Kollmann Helmut
• Roni Arif
• Stavagna Emanuele
• Wagner Christoph

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W70/654

  Top-view layouts · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title