Ic-package interconnect for millimeter wave systems

Patent metadata

Field	Value
Publication number	US-2016190673-A1
Application number	US-201414582830-A
Country	US
Kind code	A1
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having at least one differential pair pad, the at least one differential pair pad having a shunt inductor coupled thereon. A parasitic capacitance on at least one differential pair pads is tuned out by resonance of the shunt inductor. A package has a redistribution layer (RDL), with an array of contact areas to which the silicon device is mounted and then encapsulated. A connection corresponds to the at least one differential pair pad and the connection is located about an outer row or column of the array of contact areas.

First claim

1 . A method for fabricating a SoC millimeter wave device having reduced insertion loss on its differential input/output terminals, the method comprising:
determining a plurality of differential input/output terminals; measuring a capacitance of each of the plurality of the differential input/output terminals; selecting a value of inductance for a shunt inductor that is coupled to each of the plurality of the differential input/output terminals which cancels out effects of the capacitance of each of the plurality of input/output terminals; in response to selecting the value of inductance, forming a circuit layout by placing on-device shunt inductors in the vicinity of the input/output terminals, the shunt inductors coupled between the input/output terminals and a voltage or ground reference; running simulations on the circuit layout to verify whether acceptable values of shunt inductors are used, if simulations show acceptable values, generate a device design; converting the verified device design into wafer fab tooling; and fabricating silicon devices with the wafer fab tooling.

2 . The method as recited in claim 1 , wherein the value of inductance is selected so that insertion loss is less than 1 dB at a frequency range of about 76 GHz to about 81 GHz.

3 . The method as recited in claim 2 , wherein the wherein the value of inductance is selected so that insertion loss is in the range of about 0.6 dB to about 1 dB at a frequency range of about 76 GHz to about 81 GHz.

4 . The method as recited in claim 3 , wherein the value of inductance is selected so that insertion loss is about 0.75 dB at a frequency range of about 76 GHz to about 81 GHz.

5 . The method as recited in claim 1 , wherein the capacitance includes that from the silicon device, SoC packaging RDL.

6 . A System on Chip (SoC) device operating in millimeter wave frequencies, the SoC device comprising:
a silicon device having,
at least one differential pair pad having a shunt inductor coupled thereon,
wherein a parasitic capacitance on at least one differential pair pad is tuned out by resonance of the shunt inductor; and
a package having a redistribution layer (RDL), to which the silicon device is mounted and encapsulated therein, the RDL having an array of contact areas, with a connection corresponding to the at least one differential pair pad, the connection located about an outer row or column of the array of contact areas.

7 . The SoC as recited in claim 6 , wherein
the at least one differential pair pad, is either an input pad or an output pad.

8 . The SoC as recited in claim 7 , further comprising at least one differential pair input pad, and at least one differential pair output pad.

9 . The SoC device as recited in claim 8 , wherein the shunt inductor is fabricated in multiple metal layers in the at least one differential pair input pad and the at least one differential pair output pad, and the shunt inductor is coupled between the pad and ground.

10 . The SoC device as recited in claim 9 , wherein the value of the shunt inductor is chosen such that insertion loss for the at least one differential paid input pad and the at least one differential pair output pad is less than about 1 dB.

11 . The SoC device as recited in claim 10 , wherein the insertion loss is in the range of about 0.7 dB to about 0.9 dB.

12 . The SoC device as recited in claim 9 is a four receiver and three transmitter automotive radar device,
wherein each of the four receivers includes a differential input pair; and
wherein each of the three transmitters includes a differential output pair.

Assignees

• Nxp Bv

Inventors

• Huang Mingda
• Van Schie Markus Carolus Antonius

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/248

  for antennas · CPC title