Method for generating patterning device pattern at patch boundary

Patent metadata

Field	Value
Publication number	US-11797748-B2
Application number	US-201917418102-A
Country	US
Kind code	B2
Filing date	Nov 18, 2019
Priority date	Dec 28, 2018
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.

First claim

What is claimed is:

1. A method comprising:
obtaining (i) a first feature patch comprising a first polygon portion of an initial patterning device pattern, and (ii) a second feature patch comprising a second polygon portion of the initial patterning device pattern;
adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and
combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form a patterning device pattern to be employed in a patterning process.

2. The method of claim 1 , wherein the initial patterning device pattern is a design layout comprising a plurality of features to be imaged on a substrate subjected to the patterning process.

3. The method of claim 1 , wherein the first polygon portion and the second polygon portion are an aspect corresponding to a feature of the initial patterning device pattern.

4. The method of claim 3 , wherein the aspect is an assist feature corresponding to the feature, the assist feature obtained via an optical proximity correction, source optimization, and/or source-mask optimization.

5. The method of claim 1 , further comprising:
adjusting the first polygon portion at the patch boundary between the first feature patch and the second feature patch such that the difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and
determining the patterning device pattern to include a combination of the adjusted first polygon portion and the second polygon portion at the patch boundary.

6. The method of claim 1 , wherein the adjusting of the second polygon portion comprises determining a stitching function configured to seamlessly join, at the patch boundary, the first polygon portion and the second polygon portion, wherein the stitching function is a mathematical shaping function that reduces the difference between the first polygon portion and the second polygon portion at the patch boundary.

7. The method of claim 6 , wherein the difference between the first polygon portion and the second polygon portion is a step or a jump, and/or
wherein the stitching function moves polygon portions at the patch boundary to convert a step into a ramp, or a curve.

8. The method of claim 6 , wherein the stitching function is further configured to include a condition to satisfy a manufacturability check specification related to manufacturability of the patterning device pattern.

9. The method of claim 1 , wherein the initial patterning device pattern comprises a plurality of patches arranged in a sequence, each patch having a priority value within the sequence.

10. The method of claim 1 , further comprising an iterative process, an iteration of the iterative process comprising:
selecting a patch having a relatively lower priority value within a sequence of a plurality of patches;
adjusting a polygon portion within the selected patch and/or another polygon portion within an adjacent patch of the selected patch such that the difference between the polygon portions is reduced; and
generating the patterning device pattern by combining one or more patches having the same priorities with corresponding adjacent one or more patches of the plurality of patches.

11. The method of claim 1 , wherein the difference is minimized.

12. The method of claim 1 , wherein the first feature patch and the second feature patch are adjacent to each other.

13. The method of claim 1 , wherein the initial patterning device pattern and/or the patterning device pattern is a curvilinear patterning device pattern.

14. A non-transitory computer program product comprising machine-readable instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to at least:
obtain (i) a first feature patch comprising a first polygon portion of an initial patterning device pattern, and (ii) a second feature patch comprising a second polygon portion of the initial patterning device pattern;
adjust the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and
combine the first polygon portion and the adjusted second polygon portion at the patch boundary to form a patterning device pattern to be employed in a patterning process.

15. The computer program product of claim 14 , wherein the initial patterning device pattern is a design layout comprising a plurality of features to be imaged on a substrate subjected to the patterning process.

16. The computer program product of claim 14 , wherein the instructions are further configured to cause the computer system to:
adjust the first polygon portion at the patch boundary between the first feature patch and the second feature patch such that the difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and
determine the patterning device pattern to include a combination of the adjusted first polygon portion and the second polygon portion at the patch boundary.

17. The computer program product of claim 14 , wherein the instructions configured to cause the computer system to adjust the second polygon portion are further configured to cause the computer system to determine a stitching function configured to seamlessly join, at the patch boundary, the first polygon portion and the second polygon portion, wherein the stitching function is a mathematical shaping function that reduces the difference between the first polygon portion and the second polygon portion at the patch boundary.

18. The computer program product of claim 14 , wherein the initial patterning device pattern comprises a plurality of patches arranged in a sequence, each patch having a priority value within the sequence.

19. The computer program product of claim 14 , wherein the instructions are further configured to cause the computer system to iteratively:
select a patch having a relatively lower priority value within a sequence of a plurality of patches;
adjust a polygon portion within the selected patch and/or another polygon portion within an adjacent patch of the selected patch such that the difference between the polygon portions is reduced; and
generate the patterning device pattern by combination of one or more patches having the same priorities with corresponding adjacent one or more patches of the plurality of patches.

20. The computer program product of claim 14 , wherein the first feature patch and the second feature patch are adjacent to each other.

Assignees

• Asml Netherlands Bv

Inventors

• Zhang Quan
• Cho Yong-Ju
• Zhu Zhangnan
• Huang Boyang
• Chen Been-Der

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title

• G03F1/44

  Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales · CPC title