Self-aligned vertical integration of three-terminal memory devices

Patent metadata

Field	Value
Publication number	US-11792987-B2
Application number	US-201917283645-A
Country	US
Kind code	B2
Filing date	Oct 22, 2019
Priority date	Oct 26, 2018
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

First claim

What is claimed is:

1. A three-dimensional (3D) memory structure for memory cells, comprising:
a plurality of oxide layers;
a plurality of word line layers,
wherein the plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction; and
a plurality of double channel holes extending through the plurality of oxide layers and the plurality of word line layers in the first direction,
wherein the plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

2. The 3D memory structure of claim 1 , wherein the plurality of word line layers are recessed relative to the plurality of oxide layers in the plurality of double channel holes.

3. The 3D memory structure of claim 1 , wherein the memory cells further comprise three terminal NOR memory cells.

4. The 3D memory structure of claim 1 , further comprising a multilayer stack deposited on an inner surface of the plurality of double channel holes and defining a first cavity extending in the first direction.

5. The 3D memory structure of claim 4 , wherein the first cavity has a peanut-shaped cross-section in the second direction.

6. The 3D memory structure of claim 4 , wherein the multilayer stack includes a blocking oxide layer, a charge trap layer and a gate oxide layer.

7. The 3D memory structure of claim 4 , wherein the multilayer stack includes a blocking oxide layer, a ferroelectric layer and a gate oxide layer.

8. The 3D memory structure of claim 4 , wherein the multilayer stack includes a blocking oxide layer, a spin-orbit torque (SOT) layer and a gate oxide layer.

9. The 3D memory structure of claim 4 , further comprising a polysilicon layer arranged on an inner surface of the first cavity.

10. The 3D memory structure of claim 9 , wherein the polysilicon layer defines a second cavity and a third cavity extending in the first direction.

11. The 3D memory structure of claim 10 , wherein the second cavity and the third cavity have an elliptical cross-section in the second direction.

12. The 3D memory structure of claim 9 , wherein the polysilicon layer includes a P − layer.

13. The 3D memory structure of claim 9 , wherein the polysilicon layer has an “8”-shaped cross-section in the second direction.

14. The 3D memory structure of claim 10 , further comprising an N+ layer arranged in the second cavity and the third cavity.

15. A method for fabricating a three-dimensional (3D) memory structure for memory cells, comprising:
providing a substrate including a plurality of oxide layers and a plurality of nitride layers, wherein the plurality of oxide layers and the plurality of nitride layers are alternately stacked in a first direction; and
etching a plurality of double channel holes in the plurality of oxide layers and the plurality of nitride layers, wherein the plurality of double channel holes extend in the first direction,
wherein the plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

16. The method of claim 15 , wherein the memory cells comprise three terminal NOR memory cells.

17. The method of claim 15 , further comprising partially etching back the plurality of nitride layers relative to the plurality of oxide layers in the plurality of double channel holes.

18. The method of claim 17 , further comprising depositing a multilayer stack on an inner surface of the plurality of double channel holes, wherein the multilayer stack defines a first cavity extending in the first direction.

19. The method of claim 17 , wherein the first cavity has a peanut-shaped cross-section in the second direction.

20. The method of claim 18 , wherein depositing the multilayer stack includes depositing a blocking oxide layer, a charge trap layer and a gate oxide layer.

21. The method of claim 18 , wherein depositing the multilayer stack includes depositing a blocking oxide layer, a ferroelectric layer and a gate oxide layer.

22. The method of claim 18 , wherein depositing the multilayer stack includes depositing a blocking oxide layer, a spin-orbit torque (SOT) layer and a gate oxide layer.

23. The method of claim 18 , further comprising depositing a polysilicon layer on an inner surface of the first cavity in the plurality of double channel holes.

24. The method of claim 23 , wherein the polysilicon layer defines a second cavity and a third cavity extending in the first direction.

25. The method of claim 24 , wherein the second cavity and the third cavity have an elliptical cross-section in the second direction.

26. The method of claim 23 , wherein the polysilicon layer includes a P− layer.

27. The method of claim 23 , wherein the polysilicon layer has an “8”-shaped cross-section in the second direction.

28. The method of claim 24 , further comprising depositing N+ layer in the second cavity and the third cavity.

29. The method of claim 28 , further comprising cutting the substrate to at least partially expose portions of the plurality of nitride layers.

30. The method of claim 29 , further comprising etching the plurality of nitride layers.

31. The method of claim 30 , further comprising depositing conductive fill in etched locations of the plurality of nitride layers.

Assignees

• Lam Res Corp

Inventors

• Lill Thorsten
• Shen Meihua
• Hoang John
• Wu Hui-Jung
• Gunawan Gereng
• Pan Yang

Classifications

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title