Contact structures having conductive portions in substrate in three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11792980-B2
Application number	US-202117532131-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Nov 22, 2019
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a first source contact portion in a substrate, forming a dielectric stack over the first source contact portion, and forming a slit opening extending in the dielectric stack and exposing the first source contact portion. The method also includes forming a plurality of conductor layers through the slit opening and form a second source contact portion in the slit opening and in contact with the first source contact portion.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first source contact portion including a metal in a substrate;
forming a dielectric stack over the first source contact portion;
forming a slit opening extending in the dielectric stack and exposing the first source contact portion;
forming a plurality of conductor layers through the slit opening; and
forming a second source contact portion in the slit opening and in contact with the first source contact portion.

2. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first source contact portion in a substrate, comprising:
forming a source contact pattern in the substrate and extending continuously along a lateral direction; and
depositing a first conductive material including at least one of tungsten, cobalt, aluminum, and copper to fill up the source contact pattern;

forming a dielectric stack over the first source contact portion;
forming a slit opening extending in the dielectric stack and exposing the first source contact portion;
forming a plurality of conductor layers through the slit opening; and
forming a second source contact portion in the slit opening and in contact with the first source contact portion.

3. The method of claim 2 , further comprising planarizing the first conductive material to form the first source contact portion.

4. The method of claim 2 , further comprising depositing an adhesive layer in the source contact pattern before the deposition of the first conductive material.

5. The method of claim 2 , wherein forming the dielectric stack comprises forming interleaved a plurality of sacrificial layers and a plurality of dielectric layers.

6. The method of claim 5 , wherein forming the slit opening comprises forming a plurality of slit portions along the lateral direction, at least two of the slit portions being disconnected from each other along the lateral direction and each exposing the first source contact portion.

7. The method of claim 6 , wherein forming the plurality of conductor layers comprises:
removing the plurality of sacrificial layers through the slit opening to form a plurality of lateral recesses; and
depositing a conductor material to fill in the lateral recesses to form the conductor layers.

8. The method of claim 2 , wherein forming the second source contact portion comprises depositing a second conductive material in the slit opening, the second conductive material being in contact with the first conductive material at an interface coplanar with a top surface of the substrate.

9. The method of claim 8 , further comprising depositing the first conductive material above and in contact with the second conductive material in the slit opening.

10. The method of claim 2 , wherein forming the second source contact portion comprising forming a plurality of sub-contacts that are separated by an insulating spacer.

11. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first source contact portion in a substrate;
forming a dielectric stack over the first source contact portion;
forming a slit opening extending in the dielectric stack and exposing the first source contact portion;
forming a plurality of conductor layers through the slit opening; and
form a second source contact portion in the slit opening and in contact with the first source contact portion, wherein the second source contact portion including a plurality of sub-contacts that are separated by an insulating spacer.

12. The method of claim 11 , wherein forming the first source contact portion comprises:
forming a source contact pattern in the substrate and extending continuously along a lateral direction; and
depositing a first conductive material including at least one of a metal and a silicide to fill up the source contact pattern.

13. The method of claim 12 , further comprising planarizing the first conductive material to form the first source contact portion.

14. The method of claim 12 , further comprising depositing an adhesive layer in the source contact pattern before the deposition of the first conductive material.

15. The method of claim 11 , wherein forming the dielectric stack comprises forming interleaved a plurality of sacrificial layers and a plurality of dielectric layers.

16. The method of claim 15 , wherein forming the slit opening comprises forming a plurality of slit portions along the lateral direction, at least two of the slit portions being disconnected from each other along the lateral direction and each exposing the first source contact portion.

17. The method of claim 16 , wherein forming the plurality of conductor layers comprises:
removing the plurality of sacrificial layers through the slit opening to form a plurality of lateral recesses; and
depositing a conductor material to fill in the lateral recesses to form the conductor layers.

18. The method of claim 12 , wherein forming the second source contact portion comprises depositing a second conductive material in the slit opening, the second conductive material being in contact with the first conductive material at an interface coplanar with a top surface of the substrate.

19. The method of claim 18 , further comprising depositing the first conductive material above and in contact with the second conductive material in the slit opening.

20. The method of claim 14 , wherein depositing the adhesive layer comprises depositing at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xia Ji
• Xu Wei
• Huang Pan
• Xu Wenxiang
• Wang Beihan

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title