Molded semiconductor package and related methods

Patent metadata

Field	Value
Publication number	US-11791297-B2
Application number	US-202217649943-A
Country	US
Kind code	B2
Filing date	Feb 4, 2022
Priority date	Aug 17, 2017
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
one or more bumps comprised on the first side of the semiconductor die, the one or more bumps comprising a first layer and a second layer directly coupled to the first layer, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and
a mold compound encapsulating the semiconductor die on all sides of the semiconductor die, wherein a face of the one or more bumps is exposed through the mold compound;
wherein the first layer is directly coupled to the first side of the semiconductor die.

2. The semiconductor package of claim 1 , wherein the first layer is copper and the second layer is tin.

3. The semiconductor package of claim 1 , wherein the first layer is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof.

4. The semiconductor package of claim 1 , wherein the second layer is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof.

5. The semiconductor package of claim 1 , wherein the first layer is coupled between the semiconductor die and the second layer.

6. The semiconductor package of claim 1 , wherein the second layer comprises the face of the one or more bumps.

7. The semiconductor package of claim 1 , wherein a surface of the mold compound is parallel to and coplanar with the face of the one or more bumps.

8. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
one or more bumps comprised on the first side of the semiconductor die, the one or more bumps comprising a first layer comprising a first metal and a second layer comprising a second metal, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and
a mold compound encapsulating the semiconductor die on all sides of the semiconductor die;
wherein a face of the one or more bumps are exposed through the mold compound;
wherein the first layer is directly coupled to the first side of the semiconductor die; and
wherein the second layer is directly coupled to the first layer.

9. The semiconductor package of claim 8 , wherein the first metal is copper and the second metal is tin.

10. The semiconductor package of claim 8 , wherein the first metal is one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof.

11. The semiconductor package of claim 8 , wherein the second metal is one of tin, silver, gold, copper, cadmium, palladium, rhodium and any combination thereof.

12. The semiconductor package of claim 8 , wherein the first layer is coupled between the semiconductor die and the second layer.

13. The semiconductor package of claim 8 , wherein the second layer comprises the face of the one or more bumps.

14. The semiconductor package of claim 8 , wherein a surface of the mold compound is parallel to and coplanar with the face of the one or more bumps.

15. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
one or more bumps comprised on the first side of the semiconductor die, the one or more bumps comprising a first layer comprising copper and a second layer comprising tin, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and
a mold compound encapsulating all the semiconductor die on all sides of the semiconductor die;
wherein the second layer is exposed through the mold compound;
wherein the second layer is directly coupled to the first layer; and
wherein the first layer is coupled directly to the first side of the semiconductor die and is coupled between the semiconductor die and the second layer.

16. The semiconductor package of claim 15 , wherein the first layer further comprises one of silver, gold, cadmium, palladium, rhodium and any combination thereof.

17. The semiconductor package of claim 15 , wherein the second layer further comprises one of silver, gold, copper, cadmium, palladium, rhodium and any combination thereof.

18. The semiconductor package of claim 15 , wherein an outer surface of the mold compound is parallel to and coplanar with an outer most surface of the second layer of the one or more bumps.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Wang Sw
• Chew Ch
• Kurose Eiji
• Liew How Kiat

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W74/01 Primary

  Manufacture or treatment · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title